aboutsummaryrefslogtreecommitdiff
path: root/instr-table.tex
AgeCommit message (Expand)AuthorFilesLines
2011-04-06[opcodes,pk,sim,xcc] fix utidx - add rdYunsup Lee1-2/+2
2011-04-04[opcodes,pk,sim,xcc] add stop,utidx instructionsYunsup Lee1-0/+20
2011-04-04[opcodes,pk,sim,xcc] add fence instructions for vector unitYunsup Lee1-0/+36
2011-03-25[opcodes] fixed up instruction tableAndrew Waterman1-1268/+1277
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman1-13/+94
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman1-77/+43
2011-02-15[xcc,sim,opcodes] removed mtflh/mffl/mffhAndrew Waterman1-54/+0
2011-02-02[sim,xcc,opcodes] added back mtflh.dAndrew Waterman1-4/+22
2011-02-02[opcodes,pk,sim,xcc] synci now bombs whole icacheAndrew Waterman1-9/+9
2011-02-01[xcc,opcodes,pk,sim] cleanup to FP ISAAndrew Waterman1-33/+15
2011-01-25[sim,opcodes] add mulhsu instructionAndrew Waterman1-0/+9
2011-01-25[opcodes,pk,sim,xcc] great renumbering of 2011, part deuxAndrew Waterman1-62/+60
2011-01-20[sim, pk, xcc, opcodes] great instruction renaming of 2011Andrew Waterman1-577/+97
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman1-18/+0
2011-01-17[opcodes, pk, sim, xcc] removed nor, normalized macros to addiAndrew Waterman1-9/+0
2011-01-03[opcodes,pk,sim,xcc] flip fields to favor little endianYunsup Lee1-556/+1117
2010-11-21[opcodes, pk, sim, xcc] Tweaked FP encodingAndrew Waterman1-782/+544
2010-11-21[opcodes] generate latex and verilog correctlyAndrew Waterman1-855/+933
2010-11-21[xcc, sim, pk, opcodes] new instruction encoding!Andrew Waterman1-479/+398
2010-11-21[opcodes, pk, sim, xcc] made jumps shorter and PC-relativeAndrew Waterman1-8/+2
2010-10-31[opcodes] add latex table for rm stuffYunsup Lee1-464/+930
2010-10-25[sim,xcc,pk,opcodes] static rounding modes for FP insnsAndrew Waterman1-88/+16
2010-10-20[opcodes] changed formatting of optab section headersAndrew Waterman1-6/+6
2010-10-15[pk, sim] added FPU emulation support to proxy kernelAndrew Waterman1-1/+1
2010-10-07[xcc] modified opcodes for better FP decode mappingAndrew Waterman1-7/+7
2010-10-05[opcodes] added code field back to syscall/breakAndrew Waterman1-2/+2
2010-10-05[opcodes] updated parse-opcodes for latex tablesYunsup Lee1-216/+266
2010-10-05[opcodes] update parse-opcodesYunsup Lee1-307/+289
2010-10-02[xcc, sim] mff now uses rs2 for dataAndrew Waterman1-39/+39
2010-09-28[opcodes, sim, xcc] added mffl.d instructionAndrew Waterman1-274/+265
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman1-408/+408
2010-09-13[xcc, sim] replaced ble/bleu with bge/bgeuAndrew Waterman1-7/+7
2010-09-12[opcodes] fixed tex table for ish,ishw typesYunsup Lee1-96/+86
2010-09-12[sim] renamed sllv to sll (same for other shifts)Andrew Waterman1-6/+6
2010-09-12[xcc, sim] moved shamt field and renamed shiftsAndrew Waterman1-98/+98
2010-09-12[xcc, sim] branches now are next-PC-based, not PC-basedAndrew Waterman1-1/+1
2010-09-10[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bitAndrew Waterman1-2/+2
2010-09-10[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)Yunsup Lee1-0/+18
2010-09-10[opcodes] latex table generation added, new opcode mappingYunsup Lee1-0/+1752