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AgeCommit message (Expand)AuthorFilesLines
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman3-5/+47
2011-04-18[xcc,sim,opcodes] added rvc conditional branchesAndrew Waterman2-12/+16
2011-04-12[xcc,pk,sim] added privileged cflush instructionAndrew Waterman2-0/+2
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman3-4/+24
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman3-3/+10
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman3-2/+8
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman3-12/+16
2011-04-07[pk,sim] fixed parse-opcodes bugAndrew Waterman1-2/+2
2011-04-06[opcodes,pk,sim,xcc] fix utidx - add rdYunsup Lee3-4/+4
2011-04-05[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...Yunsup Lee3-92/+199
2011-04-04[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Yunsup Lee3-0/+12
2011-04-04[opcodes,pk,sim,xcc] add vector mem instructionsYunsup Lee3-0/+70
2011-04-04[opcodes,pk,sim,xcc] add stop,utidx instructionsYunsup Lee3-0/+24
2011-04-04[opcodes,pk,sim,xcc] add fence instructions for vector unitYunsup Lee3-2/+46
2011-03-25[opcodes] fixed up instruction tableAndrew Waterman2-1475/+1474
2011-03-25[opcodes] minor opcode changesAndrew Waterman2-58/+58
2011-03-25[sim,pk,xcc,opcodes] removed fminmag/fmaxmagAndrew Waterman2-8/+0
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman4-78/+181
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman3-158/+124
2011-02-15[xcc,sim,opcodes] removed mtflh/mffl/mffhAndrew Waterman3-60/+0
2011-02-02[sim,xcc,opcodes] added back mtflh.dAndrew Waterman3-6/+26
2011-02-02[opcodes,pk,sim,xcc] synci now bombs whole icacheAndrew Waterman3-11/+11
2011-02-01[xcc,opcodes,pk,sim] cleanup to FP ISAAndrew Waterman3-84/+64
2011-01-31[opcodes] fixed verilog generation for shiftsAndrew Waterman2-9/+9
2011-01-25[sim,opcodes] add mulhsu instructionAndrew Waterman3-2/+13
2011-01-25[opcodes,pk,sim,xcc] great renumbering of 2011, part deuxAndrew Waterman4-410/+402
2011-01-20[sim, pk, xcc, opcodes] great instruction renaming of 2011Andrew Waterman4-745/+271
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman3-22/+0
2011-01-17[opcodes, pk, sim, xcc] removed nor, normalized macros to addiAndrew Waterman3-11/+0
2011-01-03[opcodes,pk,sim,xcc] flip fields to favor little endianYunsup Lee4-949/+1508
2010-11-21[opcodes, pk, sim, xcc] Tweaked FP encodingAndrew Waterman4-1001/+682
2010-11-21[opcodes] generate latex and verilog correctlyAndrew Waterman4-1165/+1282
2010-11-21[xcc, sim, pk, opcodes] new instruction encoding!Andrew Waterman4-889/+812
2010-11-21[opcodes, pk, sim, xcc] made jumps shorter and PC-relativeAndrew Waterman4-18/+12
2010-10-31[opcodes] add latex table for rm stuffYunsup Lee3-560/+1111
2010-10-26[opcodes] remove .swp fileYunsup Lee1-0/+0
2010-10-25[sim,xcc,pk,opcodes] static rounding modes for FP insnsAndrew Waterman5-127/+152
2010-10-20[opcodes] changed formatting of optab section headersAndrew Waterman2-12/+12
2010-10-15[pk, sim] added FPU emulation support to proxy kernelAndrew Waterman3-2/+3
2010-10-07[xcc] modified opcodes for better FP decode mappingAndrew Waterman3-21/+21
2010-10-05[opcodes] added code field back to syscall/breakAndrew Waterman2-4/+4
2010-10-05[opcodes] updated parse-opcodes for latex tablesYunsup Lee3-278/+378
2010-10-05[opcodes] update parse-opcodesYunsup Lee3-329/+311
2010-10-02[xcc, sim] mff now uses rs2 for dataAndrew Waterman3-111/+111
2010-09-28[opcodes, sim, xcc] added mffl.d instructionAndrew Waterman3-392/+386
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman4-660/+658
2010-09-13[xcc, sim] replaced ble/bleu with bge/bgeuAndrew Waterman3-15/+15
2010-09-12[opcodes] fixed tex table for ish,ishw typesYunsup Lee3-143/+130
2010-09-12[opcodes] change rsh to ish typesYunsup Lee1-9/+9
2010-09-12[opcodes] fixed verilog generation for ish,ishw typesYunsup Lee2-14/+14
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