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2011-01-20[sim, pk, xcc, opcodes] great instruction renaming of 2011Andrew Waterman4-745/+271
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman3-22/+0
2011-01-17[opcodes, pk, sim, xcc] removed nor, normalized macros to addiAndrew Waterman3-11/+0
2011-01-03[opcodes,pk,sim,xcc] flip fields to favor little endianYunsup Lee4-949/+1508
2010-11-21[opcodes, pk, sim, xcc] Tweaked FP encodingAndrew Waterman4-1001/+682
2010-11-21[opcodes] generate latex and verilog correctlyAndrew Waterman4-1165/+1282
2010-11-21[xcc, sim, pk, opcodes] new instruction encoding!Andrew Waterman4-889/+812
2010-11-21[opcodes, pk, sim, xcc] made jumps shorter and PC-relativeAndrew Waterman4-18/+12
2010-10-31[opcodes] add latex table for rm stuffYunsup Lee3-560/+1111
2010-10-26[opcodes] remove .swp fileYunsup Lee1-0/+0
2010-10-25[sim,xcc,pk,opcodes] static rounding modes for FP insnsAndrew Waterman5-127/+152
2010-10-20[opcodes] changed formatting of optab section headersAndrew Waterman2-12/+12
2010-10-15[pk, sim] added FPU emulation support to proxy kernelAndrew Waterman3-2/+3
2010-10-07[xcc] modified opcodes for better FP decode mappingAndrew Waterman3-21/+21
2010-10-05[opcodes] added code field back to syscall/breakAndrew Waterman2-4/+4
2010-10-05[opcodes] updated parse-opcodes for latex tablesYunsup Lee3-278/+378
2010-10-05[opcodes] update parse-opcodesYunsup Lee3-329/+311
2010-10-02[xcc, sim] mff now uses rs2 for dataAndrew Waterman3-111/+111
2010-09-28[opcodes, sim, xcc] added mffl.d instructionAndrew Waterman3-392/+386
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman4-660/+658
2010-09-13[xcc, sim] replaced ble/bleu with bge/bgeuAndrew Waterman3-15/+15
2010-09-12[opcodes] fixed tex table for ish,ishw typesYunsup Lee3-143/+130
2010-09-12[opcodes] change rsh to ish typesYunsup Lee1-9/+9
2010-09-12[opcodes] fixed verilog generation for ish,ishw typesYunsup Lee2-14/+14
2010-09-12[sim] renamed sllv to sll (same for other shifts)Andrew Waterman3-18/+18
2010-09-12[xcc, sim] moved shamt field and renamed shiftsAndrew Waterman4-135/+135
2010-09-12[xcc, sim] branches now are next-PC-based, not PC-basedAndrew Waterman3-3/+3
2010-09-12add -verilog optionYunsup Lee3-0/+265
2010-09-10[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bitAndrew Waterman2-3/+3
2010-09-10[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)Yunsup Lee2-0/+20
2010-09-10[opcodes] latex table generation added, new opcode mappingYunsup Lee4-324/+2435
2010-09-09[opcodes,sim,xcc] move opcodes for 3 source instructionsYunsup Lee1-10/+10
2010-09-09Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu"Andrew Waterman1-2/+2
2010-09-07[xcc, sim] added slei/sleui in lieu of slti/sltiuAndrew Waterman1-2/+2
2010-09-06[sim, xcc] bthread threading model exposed; insn encoding cleaned upAndrew Waterman1-15/+14
2010-09-06[sim] added atomic memory operationsAndrew Waterman2-6/+23
2010-08-22[xcc,sim] added fused multiply-add and its cousinsAndrew Waterman2-0/+11
2010-08-22[xcc,sim] Eliminated slori instructionAndrew Waterman1-1/+0
2010-08-09[xcc,sim] implement FP using softfloatAndrew Waterman1-31/+30
2010-08-05[sim,xcc] Added first few Hauser FP insns (sign-injection)Andrew Waterman1-8/+17
2010-08-04[xcc] Removed ctc1, cfc1 instructions; added fp move test caseAndrew Waterman1-2/+0
2010-08-04[xcc,pk,sim] Added first part of FP supportAndrew Waterman1-6/+4
2010-08-03[sim,xcc] removed sll32/srl32/sra32 opcodesAndrew Waterman2-10/+8
2010-08-03[pk,sim,xcc] Renamed instructions to RISC-V specAndrew Waterman1-26/+26
2010-07-28[sim,xcc] Changed instruction format to RISC-VAndrew Waterman3-237/+301
2010-07-18Reorganized directory structureAndrew Waterman3-0/+267