| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2019-01-12 | Add vsetvl | Colin Schmidt | 2 | -2/+3 | |
| 2019-01-08 | vselect doesn't exist in current draft | Colin Schmidt | 1 | -3/+0 | |
| 2019-01-07 | small fixes to match doc for permutes | Colin Schmidt | 1 | -15/+10 | |
| 2018-12-24 | update for 0.6 CSRs | Colin Schmidt | 1 | -21/+1 | |
| 2018-12-22 | Fix clip wi versions | Colin Schmidt | 1 | -4/+4 | |
| 2018-12-22 | Add remaining unordered stores | Colin Schmidt | 2 | -6/+20 | |
| 2018-12-21 | separate load/store encodings | Colin Schmidt | 2 | -103/+119 | |
| 2018-12-21 | Add vsetvli encoding | Colin Schmidt | 2 | -2/+8 | |
| 2018-12-13 | Clean up comments | Colin Schmidt | 1 | -17/+3 | |
| 2018-12-13 | small cleanup | Colin Schmidt | 1 | -95/+94 | |
| 2018-12-11 | Add 0.6 encoding | Colin Schmidt | 2 | -410/+369 | |
| 2018-11-07 | Fix rvv csrs for rv32 vs rv64 | Colin Schmidt | 1 | -16/+8 | |
| 2018-11-04 | update rvv csrs | Colin Schmidt | 1 | -12/+20 | |
| 2018-11-04 | Add vsetvl to table and encoding | Colin Schmidt | 3 | -4/+5 | |
| 2018-11-01 | Add vdivu and vremu to match spec | Colin Schmidt | 2 | -10/+12 | |
| 2018-11-01 | Split vslide to vslideup/down | Colin Schmidt | 2 | -7/+8 | |
| 2018-11-01 | Add vfinsert and vfextract | Colin Schmidt | 2 | -1/+3 | |
| 2018-10-30 | Add logical shifts to follow spec | Colin Schmidt | 2 | -5/+5 | |
| 2018-10-29 | Remove fp bitmoves | Colin Schmidt | 2 | -16/+8 | |
| The bits can be reinterpreted as ints with the normal integer ops | |||||
| 2018-10-29 | add unary negation operation | Colin Schmidt | 2 | -1/+2 | |
| 2018-10-29 | Add reduction encodings | Colin Schmidt | 2 | -1/+20 | |
| 2018-10-29 | Add rgather opcode | Colin Schmidt | 2 | -1/+2 | |
| 2018-10-29 | Align comparison opcodes with spec | Colin Schmidt | 2 | -13/+19 | |
| 2018-10-29 | Add vconfig | Colin Schmidt | 2 | -0/+2 | |
| 2018-10-10 | update load/store encoding for 3 bit imm | Colin Schmidt | 2 | -266/+77 | |
| 2018-10-10 | New encoding proposal | Colin Schmidt | 3 | -125/+581 | |
| 2018-02-28 | Add csrs for v-ext in rv32 and rv64 | Colin Schmidt | 1 | -0/+24 | |
| 2018-02-09 | Updates from most recent meeting | Andrew Waterman | 2 | -7/+12 | |
| 2018-02-07 | V extension WIP | Andrew Waterman | 4 | -10/+217 | |
| 2017-12-27 | Use old C style comments. (#18) | Tim Newsome | 1 | -11/+11 | |
| This improves the chance we can use this file with older, pickier compilers. Also it makes the OpenOCD patch check script happier. | |||||
| 2017-11-27 | Rename sptbr to satp and sbadaddr to stval | Andrew Waterman | 2 | -18/+18 | |
| Closes #17 | |||||
| 2017-11-27 | Don't copy encoding.h to binutils anymore | Andrew Waterman | 1 | -4/+0 | |
| Now that binutils is upstream, we maintain that file manually. | |||||
| 2017-11-27 | Generate encoding.h for OpenOCD as well. (#16) | Tim Newsome | 1 | -2/+3 | |
| 2017-05-17 | Merge remote-tracking branch 'origin/priv-1.10' | Palmer Dabbelt | 5 | -48/+87 | |
| 2017-05-07 | SB->B; UJ->J | Andrew Waterman | 1 | -2/+2 | |
| 2017-05-07 | Add UXl/SXL | Andrew Waterman | 1 | -0/+3 | |
| 2017-04-25 | Add ECALL/EBREAK to privileged instruction table | Andrew Waterman | 1 | -0/+2 | |
| 2017-04-25 | FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X | Andrew Waterman | 3 | -4/+8 | |
| 2017-04-25 | Remove hret instruction | Andrew Waterman | 2 | -2/+1 | |
| 2017-03-31 | Add LICENSE | Andrew Waterman | 1 | -0/+24 | |
| 2017-03-31 | Support generating Go code (#3) | Benjamin Barenblat | 3 | -0/+45 | |
| * Support generating Go code Generate Go code for the RISC-V Go port <https://github.com/riscv/riscv-go>. * Clarify use of yank in Go backend * Go: Also generate funct3, csr, and funct7 encodings * Go: Emit all instructions Changes to the RISC-V Go implementation obviate the need for GO_UNUSED_INSTRUCTIONS. * Go: Print CSRs as signed values * Go: Update parse-opcodes to use obj.As See https://github.com/golang/go/commit/0d9258a830c585. * Go: Return errors out of band * Go: Return 'ok' status instead of 'err' status Also clean up imports. * Go: Make gofmt-clean * Go: Return rs2 value for each instructions Some binary floating-point instructions (ab)use the rs2 value to hold additional instruction data, so we need that data in the Go assembler. | |||||
| 2017-03-30 | New PMP encoding | Andrew Waterman | 1 | -5/+6 | |
| 2017-03-27 | Separate page faults from physical memory access exceptions | Andrew Waterman | 2 | -6/+8 | |
| 2017-03-23 | Add PMP | Andrew Waterman | 2 | -1/+32 | |
| 2017-03-23 | Add TW/TVM/TSR fields to mstatus | Andrew Waterman | 1 | -1/+4 | |
| 2017-03-09 | New counter-enable mechanism | Andrew Waterman | 1 | -2/+2 | |
| 2017-03-09 | Update SPTBR fields | Andrew Waterman | 1 | -14/+9 | |
| 2017-02-20 | Use gcc csr register constraint | Andrew Waterman | 1 | -16/+4 | |
| 2017-02-20 | Remove sfence.vm and add sfence.vma | Andrew Waterman | 2 | -6/+4 | |
| 2017-02-20 | Drop mstatus.VM field | Andrew Waterman | 1 | -1/+0 | |
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index : riscv-tools/riscv-opcodes.git | |
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