diff options
-rw-r--r-- | inst.v | 153 | ||||
-rwxr-xr-x | parse-opcodes | 111 | ||||
-rwxr-xr-x | update-opcodes | 1 |
3 files changed, 265 insertions, 0 deletions
@@ -0,0 +1,153 @@ +`define UNIMP 32'b00000000000000000000000000000000 +`define J 32'b11000_??????????????????????????? +`define JAL 32'b11001_??????????????????????????? +`define LUI 32'b1110001_?????_???????????????????? +`define BEQ 32'b1110011_?????_?????_000_???????????? +`define BNE 32'b1110011_?????_?????_001_???????????? +`define BLT 32'b1110011_?????_?????_010_???????????? +`define BLTU 32'b1110011_?????_?????_011_???????????? +`define BLE 32'b1110011_?????_?????_100_???????????? +`define BLEU 32'b1110011_?????_?????_101_???????????? +`define ADDI 32'b1110100_?????_?????_000_???????????? +`define SLTI 32'b1110100_?????_?????_001_???????????? +`define SLTIU 32'b1110100_?????_?????_010_???????????? +`define ANDI 32'b1110100_?????_?????_011_???????????? +`define ORI 32'b1110100_?????_?????_100_???????????? +`define XORI 32'b1110100_?????_?????_101_???????????? +`define ADD 32'b1110101_?????_?????_0000000000_????? +`define SUB 32'b1110101_?????_?????_0000000001_????? +`define SLT 32'b1110101_?????_?????_0000000010_????? +`define SLTU 32'b1110101_?????_?????_0000000011_????? +`define AND 32'b1110101_?????_?????_0000000100_????? +`define OR 32'b1110101_?????_?????_0000000101_????? +`define XOR 32'b1110101_?????_?????_0000000110_????? +`define NOR 32'b1110101_?????_?????_0000000111_????? +`define MUL 32'b1110101_?????_?????_0010000000_????? +`define MULH 32'b1110101_?????_?????_0010000010_????? +`define MULHU 32'b1110101_?????_?????_0010000011_????? +`define DIV 32'b1110101_?????_?????_0010000100_????? +`define DIVU 32'b1110101_?????_?????_0010000101_????? +`define REM 32'b1110101_?????_?????_0010000110_????? +`define REMU 32'b1110101_?????_?????_0010000111_????? +`define SLLV 32'b1110101_?????_?????_1000000001_????? +`define SRLV 32'b1110101_?????_?????_1000000010_????? +`define SRAV 32'b1110101_?????_?????_1000000011_????? +`define SLL 32'b1110101_00000_?????_1010_??????_????? +`define SRL 32'b1110101_00000_?????_1100_??????_????? +`define SRA 32'b1110101_00000_?????_1110_??????_????? +`define ADDIW 32'b1110110_?????_?????_000_???????????? +`define ADDW 32'b1110111_?????_?????_0000000000_????? +`define SUBW 32'b1110111_?????_?????_0000000001_????? +`define MULW 32'b1110111_?????_?????_0010000000_????? +`define MULHW 32'b1110111_?????_?????_0010000010_????? +`define MULHUW 32'b1110111_?????_?????_0010000011_????? +`define DIVW 32'b1110111_?????_?????_0010000100_????? +`define DIVUW 32'b1110111_?????_?????_0010000101_????? +`define REMW 32'b1110111_?????_?????_0010000110_????? +`define REMUW 32'b1110111_?????_?????_0010000111_????? +`define SLLVW 32'b1110111_?????_?????_1000000001_????? +`define SRLVW 32'b1110111_?????_?????_1000000010_????? +`define SRAVW 32'b1110111_?????_?????_1000000011_????? +`define SLLW 32'b1110111_00000_?????_1010_0_?????_????? +`define SRLW 32'b1110111_00000_?????_1100_0_?????_????? +`define SRAW 32'b1110111_00000_?????_1110_0_?????_????? +`define LB 32'b1111000_?????_?????_000_???????????? +`define LH 32'b1111000_?????_?????_001_???????????? +`define LW 32'b1111000_?????_?????_010_???????????? +`define LD 32'b1111000_?????_?????_011_???????????? +`define LBU 32'b1111000_?????_?????_100_???????????? +`define LHU 32'b1111000_?????_?????_101_???????????? +`define LWU 32'b1111000_?????_?????_110_???????????? +`define SYNCI 32'b1111000_00000_?????_111_???????????? +`define SB 32'b1111001_?????_?????_000_???????????? +`define SH 32'b1111001_?????_?????_001_???????????? +`define SW 32'b1111001_?????_?????_010_???????????? +`define SD 32'b1111001_?????_?????_011_???????????? +`define AMOW_ADD 32'b1111010_?????_?????_0100000000_????? +`define AMOW_SWAP 32'b1111010_?????_?????_0100000001_????? +`define AMOW_AND 32'b1111010_?????_?????_0100000010_????? +`define AMOW_OR 32'b1111010_?????_?????_0100000011_????? +`define AMOW_MIN 32'b1111010_?????_?????_0100000100_????? +`define AMOW_MAX 32'b1111010_?????_?????_0100000101_????? +`define AMOW_MINU 32'b1111010_?????_?????_0100000110_????? +`define AMOW_MAXU 32'b1111010_?????_?????_0100000111_????? +`define AMO_ADD 32'b1111010_?????_?????_0110000000_????? +`define AMO_SWAP 32'b1111010_?????_?????_0110000001_????? +`define AMO_AND 32'b1111010_?????_?????_0110000010_????? +`define AMO_OR 32'b1111010_?????_?????_0110000011_????? +`define AMO_MIN 32'b1111010_?????_?????_0110000100_????? +`define AMO_MAX 32'b1111010_?????_?????_0110000101_????? +`define AMO_MINU 32'b1111010_?????_?????_0110000110_????? +`define AMO_MAXU 32'b1111010_?????_?????_0110000111_????? +`define JALR_C 32'b1111011_?????_00000_0000000000_????? +`define JALR_R 32'b1111011_?????_00000_0000000001_????? +`define JALR_J 32'b1111011_?????_00000_0000000010_????? +`define RDPC 32'b1111011_00000_00000_0010000000_????? +`define MFCR 32'b1111011_00000_?????_0100000000_????? +`define MTCR 32'b1111011_?????_?????_0110000000_00000 +`define SYNC 32'b1111011_00000_00000_1000000000_00000 +`define SYSCALL 32'b1111011_00000_00000_1010000000_00000 +`define BREAK 32'b1111011_00000_00000_1100000000_00000 +`define EI 32'b1111110_00000_00000_0000000000_????? +`define DI 32'b1111110_00000_00000_0010000000_????? +`define ERET 32'b1111110_00000_00000_0100000000_00000 +`define MFPCR 32'b1111110_00000_?????_1000000000_????? +`define MTPCR 32'b1111110_?????_?????_1010000000_00000 +`define ADD_S 32'b1101000_?????_?????_0000000000_????? +`define SUB_S 32'b1101000_?????_?????_0000000001_????? +`define MUL_S 32'b1101000_?????_?????_0000000010_????? +`define DIV_S 32'b1101000_?????_?????_0000000011_????? +`define SQRT_S 32'b1101000_?????_00000_0000000100_????? +`define SGNINJ_S 32'b1101000_?????_?????_0000000101_????? +`define SGNINJN_S 32'b1101000_?????_?????_0000000110_????? +`define SGNMUL_S 32'b1101000_?????_?????_0000000111_????? +`define ADD_D 32'b1101000_?????_?????_1100000000_????? +`define SUB_D 32'b1101000_?????_?????_1100000001_????? +`define MUL_D 32'b1101000_?????_?????_1100000010_????? +`define DIV_D 32'b1101000_?????_?????_1100000011_????? +`define SQRT_D 32'b1101000_?????_00000_1100000100_????? +`define SGNINJ_D 32'b1101000_?????_?????_1100000101_????? +`define SGNINJN_D 32'b1101000_?????_?????_1100000110_????? +`define SGNMUL_D 32'b1101000_?????_?????_1100000111_????? +`define TRUNC_L_S 32'b1101000_?????_00000_0000100000_????? +`define TRUNCU_L_S 32'b1101000_?????_00000_0000100001_????? +`define TRUNC_W_S 32'b1101000_?????_00000_0000100010_????? +`define TRUNCU_W_S 32'b1101000_?????_00000_0000100011_????? +`define TRUNC_L_D 32'b1101000_?????_00000_1100100000_????? +`define TRUNCU_L_D 32'b1101000_?????_00000_1100100001_????? +`define TRUNC_W_D 32'b1101000_?????_00000_1100100010_????? +`define TRUNCU_W_D 32'b1101000_?????_00000_1100100011_????? +`define CVT_S_L 32'b1101000_?????_00000_0000100100_????? +`define CVTU_S_L 32'b1101000_?????_00000_0000100101_????? +`define CVT_S_W 32'b1101000_?????_00000_0000100110_????? +`define CVTU_S_W 32'b1101000_?????_00000_0000100111_????? +`define CVT_D_L 32'b1101000_?????_00000_1100100100_????? +`define CVTU_D_L 32'b1101000_?????_00000_1100100101_????? +`define CVT_D_W 32'b1101000_?????_00000_1100100110_????? +`define CVTU_D_W 32'b1101000_?????_00000_1100100111_????? +`define CVT_S_D 32'b1101000_?????_00000_0000110011_????? +`define CVT_D_S 32'b1101000_?????_00000_1100110000_????? +`define C_EQ_S 32'b1101000_?????_?????_0001000001_????? +`define C_LT_S 32'b1101000_?????_?????_0001000010_????? +`define C_LE_S 32'b1101000_?????_?????_0001000011_????? +`define C_EQ_D 32'b1101000_?????_?????_1101000001_????? +`define C_LT_D 32'b1101000_?????_?????_1101000010_????? +`define C_LE_D 32'b1101000_?????_?????_1101000011_????? +`define L_S 32'b1101001_?????_?????_000_???????????? +`define L_D 32'b1101001_?????_?????_110_???????????? +`define S_S 32'b1101001_?????_?????_001_???????????? +`define S_D 32'b1101001_?????_?????_111_???????????? +`define MFF_S 32'b1101010_?????_00000_0000000000_????? +`define MFF_D 32'b1101010_?????_00000_1100000000_????? +`define MFFH_D 32'b1101010_?????_00000_1100100000_????? +`define MTF_S 32'b1101010_?????_00000_0001000000_????? +`define MTF_D 32'b1101010_?????_00000_1101000000_????? +`define MTFLH_D 32'b1101010_?????_?????_1101100000_????? +`define MADD_S 32'b1101011_?????_?????_00000_?????_????? +`define MSUB_S 32'b1101011_?????_?????_00001_?????_????? +`define NMADD_S 32'b1101011_?????_?????_00010_?????_????? +`define NMSUB_S 32'b1101011_?????_?????_00011_?????_????? +`define MADD_D 32'b1101011_?????_?????_11000_?????_????? +`define MSUB_D 32'b1101011_?????_?????_11001_?????_????? +`define NMADD_D 32'b1101011_?????_?????_11010_?????_????? +`define NMSUB_D 32'b1101011_?????_?????_11011_?????_????? diff --git a/parse-opcodes b/parse-opcodes index 10ade79..ccf49b5 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -452,6 +452,115 @@ def make_latex_table(): print_insts(0x7e,-1,-1,-1) print_footer(1) +def str_verilog_arg(arg0,arg1,match,arguments): + if arg0 in arguments: + return '?' * (arglut[arg0][0] - arglut[arg0][1] + 1) + elif arg1 in arguments: + return '?' * (arglut[arg0][0] - arglut[arg0][1] + 1) + else: + start = arglut[arg0][1] + len = arglut[arg0][0] - arglut[arg0][1] + 1 + return binary(yank(match,start,len),len) + +def print_verilog_unimp_type(name,match,arguments): + print "`define %-10s 32'b%s" % \ + ( \ + name.replace('.','_').upper(), \ + '0'*32 \ + ) + +def print_verilog_j_type(name,match,arguments): + print "`define %-10s 32'b%s_%s" % \ + ( \ + name.replace('.','_').upper(), \ + binary(yank(match,27,5),5), \ + str_verilog_arg('imm27','',match,arguments) \ + ) + +def print_verilog_lui_type(name,match,arguments): + print "`define %-10s 32'b%s_%s_%s" % \ + ( \ + name.replace('.','_').upper(), \ + binary(yank(match,25,7),7), \ + str_verilog_arg('xa','fa',match,arguments), \ + str_verilog_arg('imm20','',match,arguments) \ + ) + +def print_verilog_i_type(name,match,arguments): + print "`define %-10s 32'b%s_%s_%s_%s_%s" % \ + ( \ + name.replace('.','_').upper(), \ + binary(yank(match,25,7),7), \ + str_verilog_arg('xa','fa',match,arguments), \ + str_verilog_arg('xb','fb',match,arguments), \ + binary(yank(match,12,3),3), \ + str_verilog_arg('imm','',match,arguments) \ + ) + +def print_verilog_rsh_type(name,match,arguments): + print "`define %-10s 32'b%s_00000_%s_%s_%s_%s" % \ + ( \ + name.replace('.','_').upper(), \ + binary(yank(match,25,7),7), \ + str_verilog_arg('xb','',match,arguments), \ + binary(yank(match,11,4),4), \ + str_verilog_arg('shamt','',match,arguments), \ + str_verilog_arg('xc','',match,arguments) \ + ) + +def print_verilog_rshw_type(name,match,arguments): + print "`define %-10s 32'b%s_00000_%s_%s_0_%s_%s" % \ + ( \ + name.replace('.','_').upper(), \ + binary(yank(match,25,7),7), \ + str_verilog_arg('xb','',match,arguments), \ + binary(yank(match,11,4),4), \ + str_verilog_arg('shamtw','',match,arguments), \ + str_verilog_arg('xc','',match,arguments) \ + ) + +def print_verilog_r4_type(name,match,arguments): + print "`define %-10s 32'b%s_%s_%s_%s_%s_%s" % \ + ( \ + name.replace('.','_').upper(), \ + binary(yank(match,25,7),7), \ + str_verilog_arg('fa','',match,arguments), \ + str_verilog_arg('fb','',match,arguments), \ + binary(yank(match,10,5),5), \ + str_verilog_arg('fd','',match,arguments), \ + str_verilog_arg('fc','',match,arguments) \ + ) + +def print_verilog_r_type(name,match,arguments): + print "`define %-10s 32'b%s_%s_%s_%s_%s" % \ + ( \ + name.replace('.','_').upper(), \ + binary(yank(match,25,7),7), \ + str_verilog_arg('xa','fa',match,arguments), \ + str_verilog_arg('xb','fb',match,arguments), \ + binary(yank(match,5,10),10), \ + str_verilog_arg('xc','fc',match,arguments) \ + ) + +def make_verilog(): + for name in namelist: + if types[name] == 0: + print_verilog_unimp_type(name,match[name],arguments[name]) + elif types[name] == 1: + print_verilog_j_type(name,match[name],arguments[name]) + elif types[name] == 2: + print_verilog_lui_type(name,match[name],arguments[name]) + elif types[name] == 3: + print_verilog_i_type(name,match[name],arguments[name]) + elif types[name] == 4: + print_verilog_r_type(name,match[name],arguments[name]) + elif types[name] == 5: + print_verilog_r4_type(name,match[name],arguments[name]) + elif types[name] == 6: + print_verilog_rsh_type(name,match[name],arguments[name]) + elif types[name] == 7: + print_verilog_rshw_type(name,match[name],arguments[name]) + for line in sys.stdin: line = line.partition('#') tokens = line[0].split() @@ -514,6 +623,8 @@ for line in sys.stdin: if sys.argv[1] == '-tex': make_latex_table() +elif sys.argv[1] == '-verilog': + make_verilog() elif sys.argv[1] == '-disasm': make_disasm_table(match,mask) elif sys.argv[1] == '-switch': diff --git a/update-opcodes b/update-opcodes index be3d2cc..1424ef5 100755 --- a/update-opcodes +++ b/update-opcodes @@ -1,4 +1,5 @@ #!/bin/bash ./parse-opcodes -tex < opcodes > instr-table.tex +./parse-opcodes -verilog < opcodes > inst.v ./parse-opcodes -disasm < opcodes > ../xcc/src/include/opcode/mips-riscv-opc.h ./parse-opcodes -switch < opcodes > ../sim/riscv/execute.h |