diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | opcodes-rvc | 55 | ||||
| -rw-r--r-- | opcodes-rvc-pseudo | 30 |
3 files changed, 65 insertions, 22 deletions
@@ -8,7 +8,7 @@ ENV_H := ../riscv-tests/env/encoding.h GAS_H := ../riscv-gnu-toolchain/binutils/include/opcode/riscv-opc.h XCC_H := ../riscv-gnu-toolchain/gcc/gcc/config/riscv/riscv-opc.h -ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-hwacha opcodes-hwacha-pseudo opcodes-hwacha-ut opcodes-custom +ALL_OPCODES := opcodes opcodes-pseudo opcodes-rvc opcodes-rvc-pseudo opcodes-hwacha opcodes-hwacha-pseudo opcodes-hwacha-ut opcodes-custom install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(GAS_H) $(XCC_H) inst.chisel instr-table.tex priv-instr-table.tex diff --git a/opcodes-rvc b/opcodes-rvc index 720d1ba..36dcdd4 100644 --- a/opcodes-rvc +++ b/opcodes-rvc @@ -1,24 +1,37 @@ # compressed instructions -c.li 1..0=0 15..13=0 12=ignore 11..2=ignore -c.lui 1..0=0 15..13=1 12=ignore 11..2=ignore -c.addi 1..0=0 15..13=4 12=ignore 11..2=ignore -c.addiw 1..0=0 15..13=7 12=ignore 11..2=ignore -c.slli 1..0=0 15..13=6 12=ignore 11..2=ignore -c.addi4 1..0=0 15..13=5 12=ignore 11..2=ignore -c.mv 1..0=0 15..13=2 12=0 11..2=ignore -c.jalr 1..0=0 15..13=2 12=1 11..2=ignore -c.add 1..0=0 15..13=3 12=0 11..2=ignore -c.addw 1..0=0 15..13=3 12=1 11..2=ignore -c.lw 1..0=1 15..13=0 12=ignore 11..2=ignore -c.sw 1..0=1 15..13=2 12=ignore 11..2=ignore -c.ld 1..0=1 15..13=1 12=ignore 11..2=ignore -c.sd 1..0=1 15..13=3 12=ignore 11..2=ignore -c.lwsp 1..0=1 15..13=4 12=ignore 11..2=ignore -c.ldsp 1..0=1 15..13=6 12=ignore 11..2=ignore -c.swsp 1..0=1 15..13=5 12=ignore 11..2=ignore -c.sdsp 1..0=1 15..13=7 12=ignore 11..2=ignore +# C0 encoding space +c.mv 1..0=0 15..13=0 12=0 11..2=ignore +c.add 1..0=0 15..13=0 12=1 11..2=ignore # c.ebreak when rd=0, rs2=0 +c.srai 1..0=0 15..13=1 12=ignore 11..2=ignore +c.sw 1..0=0 15..13=2 12=ignore 11..2=ignore +c.sd 1..0=0 15..13=3 12=ignore 11..2=ignore +c.sub 1..0=0 15..13=4 12=0 11..2=ignore +c.addw 1..0=0 15..13=4 12=1 11..2=ignore +c.add3 1..0=0 15..13=5 12..7=ignore 6..5=0 4..2=ignore +c.sub3 1..0=0 15..13=5 12..7=ignore 6..5=1 4..2=ignore +c.or3 1..0=0 15..13=5 12..7=ignore 6..5=2 4..2=ignore +c.and3 1..0=0 15..13=5 12..7=ignore 6..5=3 4..2=ignore +c.lw 1..0=0 15..13=6 12=ignore 11..2=ignore +c.ld 1..0=0 15..13=7 12=ignore 11..2=ignore -c.beqz 1..0=2 15..13=1 12=ignore 11..2=ignore -c.bnez 1..0=2 15..13=3 12=ignore 11..2=ignore -c.j 1..0=2 15..13=5 12=ignore 11..2=ignore + +# C1 encoding space +c.slli 1..0=1 15..13=0 12=ignore 11..2=ignore +c.srli 1..0=1 15..13=1 12=ignore 11..2=ignore +c.swsp 1..0=1 15..13=2 12=ignore 11..2=ignore +c.sdsp 1..0=1 15..13=3 12=ignore 11..2=ignore +c.slliw 1..0=1 15..13=4 12=ignore 11..2=ignore +c.addi4spn 1..0=1 15..13=5 12=ignore 11..2=ignore +c.lwsp 1..0=1 15..13=6 12=ignore 11..2=ignore +c.ldsp 1..0=1 15..13=7 12=ignore 11..2=ignore + +# C2 encoding space +c.j 1..0=2 15..13=0 12=ignore 11..2=ignore +c.jal 1..0=2 15..13=1 12=ignore 11..2=ignore +c.beqz 1..0=2 15..13=2 12=ignore 11..2=ignore +c.bnez 1..0=2 15..13=3 12=ignore 11..2=ignore +c.li 1..0=2 15..13=4 12=ignore 11..2=ignore # c.jr when simm=0 +c.lui 1..0=2 15..13=5 12=ignore 11..2=ignore # c.jalr when simm=0 +c.addi 1..0=2 15..13=6 12=ignore 11..2=ignore # c.addi16sp when rd=0 +c.addiw 1..0=2 15..13=7 12=ignore 11..2=ignore diff --git a/opcodes-rvc-pseudo b/opcodes-rvc-pseudo new file mode 100644 index 0000000..cdc0127 --- /dev/null +++ b/opcodes-rvc-pseudo @@ -0,0 +1,30 @@ +# these aren't really pseudo-ops, but they overlay other encodings, +# so they are here to prevent parse-opcodes from barfing + +@c.ebreak 1..0=0 15..13=0 12=1 11..7=0 6..2=0 +@c.jr 1..0=2 15..13=4 12=0 11..7=ignore 6..2=0 +@c.jalr 1..0=2 15..13=5 12=0 11..7=ignore 6..2=0 +@c.addi16sp 1..0=2 15..13=6 12=ignore 11..7=0 6..2=ignore + +# C0 encoding space, RV32C-only +@c.xor 1..0=0 15..13=3 12..10=0 9..7=ignore 6..5=0 4..2=ignore +@c.sra 1..0=0 15..13=3 12..10=0 9..7=ignore 6..5=1 4..2=ignore +@c.sll 1..0=0 15..13=3 12..10=1 9..7=ignore 6..5=0 4..2=ignore +@c.srl 1..0=0 15..13=3 12..10=1 9..7=ignore 6..5=1 4..2=ignore +@c.slt 1..0=0 15..13=3 12..10=1 9..7=ignore 6..5=2 4..2=ignore +@c.sltu 1..0=0 15..13=3 12..10=1 9..7=ignore 6..5=3 4..2=ignore +@c.sllr 1..0=0 15..13=3 12..10=3 9..7=ignore 6..5=0 4..2=ignore +@c.srlr 1..0=0 15..13=3 12..10=3 9..7=ignore 6..5=1 4..2=ignore +@c.sltr 1..0=0 15..13=3 12..10=3 9..7=ignore 6..5=2 4..2=ignore +@c.sltur 1..0=0 15..13=3 12..10=3 9..7=ignore 6..5=3 4..2=ignore + +# C1 encoding space, RV32C-only +@c.bltz 1..0=1 15..13=3 12=ignore 11..2=ignore +@c.bgez 1..0=1 15..13=7 12=ignore 11..2=ignore +@c.addin 1..0=1 15..13=4 12..10=ignore 9..7=ignore 6..5=0 4..2=ignore +@c.xorin 1..0=1 15..13=4 12..10=ignore 9..7=ignore 6..5=1 4..2=ignore +@c.orin 1..0=1 15..13=4 12..10=ignore 9..7=ignore 6..5=2 4..2=ignore +@c.andin 1..0=1 15..13=4 12..10=ignore 9..7=ignore 6..5=3 4..2=ignore + +# C2 encoding space, RV32C-only +@c.andi 1..0=2 15..13=7 12=ignore 11..2=ignore |