diff options
-rw-r--r-- | Makefile | 4 | ||||
-rw-r--r-- | opcodes | 4 | ||||
-rw-r--r-- | opcodes-v | 81 | ||||
-rwxr-xr-x | parse-opcodes | 138 |
4 files changed, 217 insertions, 10 deletions
@@ -6,7 +6,7 @@ FESVR_H := ../riscv-fesvr/fesvr/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h -ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom +ALL_OPCODES := opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-v install: $(ISASIM_H) $(PK_H) $(FESVR_H) $(ENV_H) $(OPENOCD_H) inst.chisel instr-table.tex priv-instr-table.tex @@ -21,7 +21,7 @@ inst.go: opcodes opcodes-pseudo parse-opcodes cat opcodes opcodes-pseudo | ./parse-opcodes -go > $@ instr-table.tex: $(ALL_OPCODES) parse-opcodes - cat opcodes opcodes-pseudo | ./parse-opcodes -tex > $@ + cat opcodes opcodes-pseudo opcodes-v | ./parse-opcodes -tex > $@ priv-instr-table.tex: $(ALL_OPCODES) parse-opcodes cat opcodes opcodes-pseudo | ./parse-opcodes -privtex > $@ @@ -221,11 +221,11 @@ fmv.q.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=3 6..2=0x14 1..0=3 flw rd rs1 imm12 14..12=2 6..2=0x01 1..0=3 fld rd rs1 imm12 14..12=3 6..2=0x01 1..0=3 -flq rd rs1 imm12 14..12=4 6..2=0x01 1..0=3 +@flq rd rs1 imm12 14..12=4 6..2=0x01 1..0=3 fsw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x09 1..0=3 fsd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x09 1..0=3 -fsq imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x09 1..0=3 +@fsq imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x09 1..0=3 fmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x10 1..0=3 fmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x11 1..0=3 diff --git a/opcodes-v b/opcodes-v new file mode 100644 index 0000000..60089aa --- /dev/null +++ b/opcodes-v @@ -0,0 +1,81 @@ +# Vector loads & stores +vld m vd rs1 24..20=0 vlimm 26..25=0 14=1 6..0=0x07 +vlds m vd rs1 rs2 vlimm 26..25=1 14=1 6..0=0x07 +vldx m vd rs1 vs2 vlimm 26..25=2 14=1 6..0=0x07 +vst m vs3 rs1 24..20=0 vsimm 26..25=0 14=1 6..0=0x27 +vsts m vs3 rs1 rs2 vsimm 26..25=1 14=1 6..0=0x27 +vstx m vs3 rs1 vs2 vsimm 26..25=2 14=1 6..0=0x27 + +# Vector AMOs +vamoswap m vd vs3 vs2 19..15=0x01 26..25=3 14=1 6..0=0x27 +vamoadd m vd vs3 vs2 19..15=0x00 26..25=3 14=1 6..0=0x27 +vamoxor m vd vs3 vs2 19..15=0x04 26..25=3 14=1 6..0=0x27 +vamoor m vd vs3 vs2 19..15=0x08 26..25=3 14=1 6..0=0x27 +vamoand m vd vs3 vs2 19..15=0x0C 26..25=3 14=1 6..0=0x27 +vamomin m vd vs3 vs2 19..15=0x10 26..25=3 14=1 6..0=0x27 +vamomax m vd vs3 vs2 19..15=0x14 26..25=3 14=1 6..0=0x27 + +# Vector FMA +@vmadd m vd vs1 vs2 vs3 26..25=0 14=0 6..0=0x67 +@vmsub m vd vs1 vs2 vs3 26..25=1 14=0 6..0=0x67 +@vnmsub m vd vs1 vs2 vs3 26..25=2 14=0 6..0=0x67 +@vnmadd m vd vs1 vs2 vs3 26..25=3 14=0 6..0=0x67 + +# Vector arithmetic. +# First, all the immediates. +vaddi m vd vs1 vimm 31..28=0 14=1 6..0=0x67 +vsli m vd vs1 vimm 31..28=1 14=1 6..0=0x67 +vcvti m vd vs1 vimm 31..28=2 14=1 6..0=0x67 +vclipi m vd vs1 vimm 31..28=3 14=1 6..0=0x67 +vxori m vd vs1 vimm 31..28=4 14=1 6..0=0x67 +vsri m vd vs1 vimm 31..28=5 14=1 6..0=0x67 +vori m vd vs1 vimm 31..28=6 14=1 6..0=0x67 +vandi m vd vs1 vimm 31..28=7 14=1 6..0=0x67 + +# group 31..28=8 +vadd m vd vs1 vs2 27..25=0 31..28=8 14=1 6..0=0x67 +vsub m vd vs1 vs2 27..25=1 31..28=8 14=1 6..0=0x67 +vmin m vd vs1 vs2 27..25=2 31..28=8 14=1 6..0=0x67 +vmax m vd vs1 vs2 27..25=3 31..28=8 14=1 6..0=0x67 +vdiv m vd vs1 vs2 27..25=4 31..28=8 14=1 6..0=0x67 +vrem m vd vs1 vs2 27..25=5 31..28=8 14=1 6..0=0x67 +vmul m vd vs1 vs2 27..25=6 31..28=8 14=1 6..0=0x67 +vmulh m vd vs1 vs2 27..25=7 31..28=8 14=1 6..0=0x67 + +# group 31..28=9 +vsl m vd vs1 vs2 27..25=0 31..28=9 14=1 6..0=0x67 +vsgnjx m vd vs1 vs2 27..25=1 31..28=9 14=1 6..0=0x67 +vsgnj m vd vs1 vs2 27..25=2 31..28=9 14=1 6..0=0x67 +vsgnjn m vd vs1 vs2 27..25=3 31..28=9 14=1 6..0=0x67 +vseq m vd vs1 vs2 27..25=4 31..28=9 14=1 6..0=0x67 +vsne m vd vs1 vs2 27..25=5 31..28=9 14=1 6..0=0x67 +vslt m vd vs1 vs2 27..25=6 31..28=9 14=1 6..0=0x67 +vsge m vd vs1 vs2 27..25=7 31..28=9 14=1 6..0=0x67 + +# group 31..28=10 includes instructions that write xd +# (and may also read xs1 and/or xs2). +vextract m rd vs1 rs2 27..25=1 31..28=10 14=1 6..0=0x67 + +# group 31..28=11 includes instructions that read xs1 and/or xs2, +# but do not write xd. +vclip m vd vs1 rs2 27..25=0 31..28=11 14=1 6..0=0x67 +vinsert m vd rs1 rs2 27..25=1 31..28=11 14=1 6..0=0x67 +vslide m vd rs1 rs2 27..25=2 31..28=11 14=1 6..0=0x67 + +# group 31..28=12 +vxor m vd vs1 vs2 27..25=0 31..28=12 14=1 6..0=0x67 +vmerge m vd vs1 vs2 27..25=1 31..28=12 14=1 6..0=0x67 +vselect m vd vs1 vs2 27..25=2 31..28=12 14=1 6..0=0x67 +# group 31..28=12, 27..25=7 is for single-argument instructions. +vclass m vd vs1 27..25=7 31..28=12 14=1 6..0=0x67 24..20=0 +vpopc m vd vs1 27..25=7 31..28=12 14=1 6..0=0x67 24..20=1 +vsqrt m vd vs1 27..25=7 31..28=12 14=1 6..0=0x67 24..20=2 + +# group 31..28=13 +vsr m vd vs1 vs2 27..25=0 31..28=13 14=1 6..0=0x67 + +# group 31..28=14 +vor m vd vs1 vs2 27..25=0 31..28=14 14=1 6..0=0x67 + +# group 31..28=15 +vand m vd vs1 vs2 27..25=0 31..28=15 14=1 6..0=0x67 diff --git a/parse-opcodes b/parse-opcodes index 1d24c77..d13fe6d 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -29,7 +29,15 @@ arglut['bimm12lo'] = (11,7) arglut['zimm'] = (19,15) arglut['shamt'] = (25,20) arglut['shamtw'] = (24,20) -arglut['vseglen'] = (31,29) + +arglut['vd'] = (11,7) +arglut['vs1'] = (19,15) +arglut['vs2'] = (24,20) +arglut['vs3'] = (31,27) +arglut['m'] = (13,12) +arglut['vimm'] = (27,20) +arglut['vlimm'] = (31,27) +arglut['vsimm'] = (11,7) causes = [ (0x00, 'misaligned fetch'), @@ -584,6 +592,79 @@ def print_fence_type(name,match,arguments): str_inst(name,arguments) \ ) +def print_vi_type(name,match,arguments): + print """ +& +\\multicolumn{1}{|c|}{%s} & +\\multicolumn{3}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-10} + """ % \ + ( \ + binary(yank(match,28,4),4), \ + str_arg('vimm','imm[7:0]',match,arguments), \ + str_arg('vs1','',match,arguments), \ + binary(yank(match,14,1),1), \ + str_arg('m','',match,arguments), \ + str_arg('vd','',match,arguments), \ + binary(yank(match,opcode_base,opcode_size),opcode_size), \ + str_inst(name,arguments) \ + ) + +def print_vs_type(name,match,arguments): + print """ +& +\\multicolumn{2}{|c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-10} + """ % \ + ( \ + 'vlimm' in arguments and 'imm[4:0]' or str_arg('vs3','',match,arguments), \ + binary(yank(match,25,2),2), \ + str_arg('rs2' in arguments and 'rs2' or 'vs2','',match,arguments), \ + str_arg('rs1','',match,arguments), \ + binary(yank(match,14,1),1), \ + str_arg('m','',match,arguments), \ + 'vsimm' in arguments and 'imm[4:0]' or str_arg('vd','',match,arguments), \ + binary(yank(match,opcode_base,opcode_size),opcode_size), \ + str_inst(name,arguments) \ + ) + +def print_vr_type(name,match,arguments): + print """ +& +\\multicolumn{1}{|c|}{%s} & +\\multicolumn{2}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & +\\multicolumn{1}{c|}{%s} & %s \\\\ +\\cline{2-10} + """ % \ + ( \ + binary(yank(match,28,4),4), \ + binary(yank(match,25,3),3), \ + str_arg('rs2' in arguments and 'rs2' or 'vs2','',match,arguments), \ + str_arg('rs1' in arguments and 'rs1' or 'vs1','',match,arguments), \ + binary(yank(match,14,1),1), \ + str_arg('m','',match,arguments), \ + str_arg('rd' in arguments and 'rd' or 'vd','',match,arguments), \ + binary(yank(match,opcode_base,opcode_size),opcode_size), \ + str_inst(name,arguments) \ + ) + def print_header(*types): print """ \\newpage @@ -678,14 +759,36 @@ def print_header(*types): \\cline{2-11} """ -def print_subtitle(title): +def print_subtitle(title, fields=10): print """ & -\\multicolumn{10}{c}{} & \\\\ +\\multicolumn{%d}{c}{} & \\\\ & -\\multicolumn{10}{c}{\\bf %s} & \\\\ -\\cline{2-11} - """ % title +\\multicolumn{%d}{c}{\\bf %s} & \\\\ +\\cline{2-%d} + """ % (fields, fields, title, fields+1) + +def print_vector_header(): + print """ +\\newpage + +\\begin{table}[p] +\\begin{small} +\\begin{center} +\\begin{tabular}{p{0in}p{0.4in}p{0.1in}p{0.3in}p{0.5in}p{0.5in}p{0.1in}p{0.3in}p{0.5in}p{0.7in}l} +& & & & & & & & & \\\\ + & +\\instbitrange{31}{28} & +\\instbit{27} & +\\instbitrange{26}{25} & +\\instbitrange{24}{20} & +\\instbitrange{19}{15} & +\\instbit{14} & +\\instbitrange{13}{12} & +\\instbitrange{11}{7} & +\\instbitrange{6}{0} \\\\ +\\cline{2-10} +""" def print_footer(caption=''): print """ @@ -720,6 +823,12 @@ def print_inst(n): print_sb_type(n, match[n], arguments[n]) elif 'rs3' in arguments[n]: print_r4_type(n, match[n], arguments[n]) + elif 'vimm' in arguments[n]: + print_vi_type(n, match[n], arguments[n]) + elif 'vlimm' in arguments[n] or 'vs3' in arguments[n]: + print_vs_type(n, match[n], arguments[n]) + elif 'vs1' in arguments[n] or 'vs2' in arguments[n] or 'vd' in arguments[n]: + print_vr_type(n, match[n], arguments[n]) else: print_r_type(n, match[n], arguments[n]) @@ -803,6 +912,23 @@ def make_latex_table(): print_subtitle('RV64D Standard Extension (in addition to RV32D)') print_insts('fcvt.l.d', 'fcvt.lu.d', 'fmv.x.d') print_insts('fcvt.d.l', 'fcvt.d.lu', 'fmv.d.x') + print_footer() + + print_vector_header() + print_subtitle('RV32V Standard Extension', 9) + print_insts('vadd', 'vsub', 'vsl', 'vsr', 'vand', 'vor', 'vxor') + print_insts('vseq', 'vsne', 'vslt', 'vsge') + print_insts('vclip', 'vinsert', 'vextract', 'vmerge', 'vselect', 'vslide') + print_insts('vdiv', 'vrem', 'vmul', 'vmulh') + print_insts('vmin', 'vmax', 'vsgnj', 'vsgnjn', 'vsgnjx') + print_insts('vsqrt', 'vclass') + print_insts('vpopc') + print_insts('vcvti', 'vaddi', 'vsli', 'vsri', 'vandi', 'vori', 'vxori') + print_insts('vclipi') + print_insts('vmadd', 'vmsub', 'vnmadd', 'vnmsub') + print_insts('vld', 'vlds', 'vldx') + print_insts('vst', 'vsts', 'vstx') + print_insts('vamoswap', 'vamoadd', 'vamoand', 'vamoor', 'vamoxor', 'vamomin', 'vamomax') print_footer('\\caption{Instruction listing for RISC-V}') def print_chisel_insn(name): |