New encoding proposal

1 files changed, 138 insertions, 76 deletions

diff --git a/parse-opcodes b/parse-opcodes
index 42677cf..1617ec2 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -36,8 +36,8 @@ arglut['vs2'] = (24,20)
 arglut['vs3'] = (31,27)
 arglut['m'] = (13,12)
 arglut['vimm'] = (27,20)
-arglut['vlimm'] = (31,27)
-arglut['vsimm'] = (11,7)
+arglut['vlimm'] = (31,31)
+arglut['vsimm'] = (11,10)
 
 causes = [
   (0x00, 'misaligned fetch'),
@@ -617,17 +617,7 @@ def print_fence_type(name,match,arguments):
   )
 
 def print_vi_type(name,match,arguments):
-  print """
-&
-\\multicolumn{1}{|c|}{%s} &
-\\multicolumn{3}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} & %s \\\\
-\\cline{2-10}
-  """ % \
+  print """2+|%s 3+|%s|%s|%s|%s 2+|%s|%s|%s""" % \
   ( \
     binary(yank(match,28,4),4), \
     str_arg('vimm','imm[7:0]',match,arguments), \
@@ -640,43 +630,51 @@ def print_vi_type(name,match,arguments):
   )
 
 def print_vs_type(name,match,arguments):
-  print """
-&
-\\multicolumn{2}{|c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} & %s \\\\
-\\cline{2-10}
-  """ % \
+  print """3+|%s|%s|%s|%s|%s|%s|%s|%s|%s|%s""" % \
+  ( \
+    'vlimm' in arguments and 'imm[0]' or str_arg('vs3','',match,arguments), \
+    binary(yank(match,25,2),2), \
+    str_arg('rs2' in arguments and 'rs2' or 'vs2','',match,arguments), \
+    str_arg('rs1' in arguments and 'rs1' or 'vs1','',match,arguments), \
+    binary(yank(match,14,1),1), \
+    str_arg('m','',match,arguments), \
+    'vsimm' in arguments and 'imm[1:0]' or str_arg('vd','',match,arguments), \
+    binary(yank(match,7,3),3), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_vl_type(name,match,arguments):
+  print """|%s 2+|%s|%s|%s|%s|%s|%s 2+|%s|%s|%s""" % \
+  ( \
+    'vlimm' in arguments and 'imm[0]' or str_arg('vs3','',match,arguments), \
+    binary(yank(match,27,4),4), \
+    binary(yank(match,25,2),2), \
+    str_arg('rs2' in arguments and 'rs2' or 'vs2','',match,arguments), \
+    str_arg('rs1' in arguments and 'rs1' or 'vs1','',match,arguments), \
+    binary(yank(match,14,1),1), \
+    str_arg('m','',match,arguments), \
+    'vsimm' in arguments and 'imm[1:0]' or str_arg('vd','',match,arguments), \
+    binary(yank(match,opcode_base,opcode_size),opcode_size), \
+    str_inst(name,arguments) \
+  )
+
+def print_vr4_type(name,match,arguments):
+  print """ 2+|%s 2+|%s|%s|%s|%s|%s 2+|%s|%s|%s""" % \
   ( \
-    'vlimm' in arguments and 'imm[4:0]' or str_arg('vs3','',match,arguments), \
+    str_arg('rs3' in arguments and 'rs3' or 'vs3','',match,arguments), \
     binary(yank(match,25,2),2), \
     str_arg('rs2' in arguments and 'rs2' or 'vs2','',match,arguments), \
     str_arg('rs1' in arguments and 'rs1' or 'vs1','',match,arguments), \
     binary(yank(match,14,1),1), \
     str_arg('m','',match,arguments), \
-    'vsimm' in arguments and 'imm[4:0]' or str_arg('vd','',match,arguments), \
+    str_arg('rd' in arguments and 'rd' or 'vd','',match,arguments), \
     binary(yank(match,opcode_base,opcode_size),opcode_size), \
     str_inst(name,arguments) \
   )
 
 def print_vr_type(name,match,arguments):
-  print """
-&
-\\multicolumn{1}{|c|}{%s} &
-\\multicolumn{2}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} &
-\\multicolumn{1}{c|}{%s} & %s \\\\
-\\cline{2-10}
-  """ % \
+  print """ 2+|%s 2+|%s|%s|%s|%s|%s 2+|%s|%s|%s""" % \
   ( \
     binary(yank(match,28,4),4), \
     binary(yank(match,25,3),3), \
@@ -792,28 +790,40 @@ def print_subtitle(title, fields=10):
 \\cline{2-%d}
   """ % (fields, fields, title, fields+1)
 
-def print_vector_header():
+def print_vec_subtitle(title):
+  print "===%s===" % (title)
+
+def print_vec_header():
   print """
-\\newpage
+.Vector Table
+[width="100%",cols="1,3,1,2,5,5,1,2,2,3,7,10"]
+|========================
+|31 |30   28 |27 |26 25 |24  20 |19    15 |14 |13 12 |11 10 |9  7 |6  0 |Opcode
+"""
 
-\\begin{table}[p]
-\\begin{small}
-\\begin{center}
-\\begin{tabular}{p{0in}p{0.4in}p{0.1in}p{0.3in}p{0.5in}p{0.5in}p{0.1in}p{0.3in}p{0.5in}p{0.7in}l}
-& & & & & & & & & \\\\
-                      &
-\\instbitrange{31}{28} &
-\\instbit{27} &
-\\instbitrange{26}{25} &
-\\instbitrange{24}{20} &
-\\instbitrange{19}{15} &
-\\instbit{14} &
-\\instbitrange{13}{12} &
-\\instbitrange{11}{7} &
-\\instbitrange{6}{0} \\\\
-\\cline{2-10}
+def print_vec_footer():
+  print """
+|========================
 """
 
+def print_vec_inst(n):
+  if 'vimm' in arguments[n]:
+    print_vi_type(n, match[n], arguments[n])
+  elif 'vsimm' in arguments[n]:
+    print_vs_type(n, match[n], arguments[n])
+  elif 'vlimm' in arguments[n]:
+    print_vl_type(n, match[n], arguments[n])
+  elif 'vs3' in arguments[n]:
+    print_vr4_type(n, match[n], arguments[n])
+  elif 'vs1' in arguments[n] or 'vs2' in arguments[n] or 'vd' in arguments[n]:
+    print_vr_type(n, match[n], arguments[n])
+  else:
+    print_r_type(n, match[n], arguments[n])
+
+def print_vec_insts(*names):
+  for n in names:
+    print_vec_inst(n)
+
 def print_footer(caption=''):
   print """
 \\end{tabular}
@@ -938,25 +948,75 @@ def make_latex_table():
   print_insts('fcvt.d.l', 'fcvt.d.lu', 'fmv.d.x')
   print_footer()
 
-  print_vector_header()
-  print_subtitle('RV32V Standard Extension', 9)
-  print_insts('vadd', 'vsub', 'vsl', 'vsr', 'vand', 'vor', 'vxor')
-  print_insts('vseq', 'vsne', 'vslt', 'vsge')
-  print_insts('vclip', 'vcvt', 'vmpop', 'vmfirst', 'vextract', 'vinsert', 'vmerge', 'vselect', 'vslide')
-  print_insts('vdiv', 'vrem', 'vmul', 'vmulh')
-  print_insts('vmin', 'vmax', 'vsgnj', 'vsgnjn', 'vsgnjx')
-  print_insts('vsqrt', 'vclass')
-  print_insts('vpopc')
-  print_insts('vaddi', 'vsli', 'vsri', 'vandi', 'vori', 'vxori')
-  print_insts('vclipi')
-  print_insts('vmadd', 'vmsub', 'vnmadd', 'vnmsub')
-  print_footer()
-  print_vector_header()
-  print_subtitle('RV32V Standard Extension (cont.)', 9)
-  print_insts('vld', 'vlds', 'vldx')
-  print_insts('vst', 'vsts', 'vstx')
-  print_insts('vamoswap', 'vamoadd', 'vamoand', 'vamoor', 'vamoxor', 'vamomin', 'vamomax')
-  print_footer('\\caption{Instruction listing for RISC-V}')
+def make_vector_adoc_table():
+  #print_vec_subtitile('RV32V Standard Extension')
+  print_vec_header()
+  print_vec_insts('vadd', 'vsub', 'vsl', 'vsr', 'vand', 'vor', 'vxor')
+  print_vec_insts('vseq', 'vsne', 'vslt', 'vsge')
+  print_vec_insts('vclip', 'vcvt', 'vmpop', 'vmfirst', 'vextract', 'vinsert', 'vmerge', 'vselect', 'vslide')
+  print_vec_insts('vdiv', 'vrem', 'vmul', 'vmulh', 'vmulhu', 'vmulhsu')
+  print_vec_insts('vpopc')
+  print_vec_insts('vaddi', 'vsli', 'vsrli', 'vsrai', 'vclipi', 'vandi', 'vori', 'vxori')
+  print_vec_footer()
+  print_vec_header()
+  print_vec_insts('vfmadd.s', 'vfmsub.s')
+  print_vec_insts('vfadd.s', 'vfsub.s', 'vfmul.s', 'vfdiv.s', 'vfsqrt.s')
+  print_vec_insts('vfsgnj.s', 'vfsgnjn.s', 'vfsgnjx.s', 'vfmin.s', 'vfmax.s')
+  print_vec_insts('vfeq.s', 'vflt.s', 'vfle.s', 'vfclass.s')
+  print_vec_insts('vfcvt.w.s', 'vfcvt.wu.s', 'vfmv.x.w')
+  print_vec_insts('vfcvt.s.w', 'vfcvt.s.wu', 'vfmv.w.x')
+  print_vec_insts('vfcvt.l.s', 'vfcvt.lu.s')
+  print_vec_insts('vfcvt.s.l', 'vfcvt.s.lu')
+  print_vec_footer()
+  print_vec_header()
+  print_vec_insts('vfmadd.d', 'vfmsub.d')
+  print_vec_insts('vfadd.d', 'vfsub.d', 'vfmul.d', 'vfdiv.d', 'vfsqrt.d')
+  print_vec_insts('vfsgnj.d', 'vfsgnjn.d', 'vfsgnjx.d', 'vfmin.d', 'vfmax.d')
+  print_vec_insts('vfeq.d', 'vflt.d', 'vfle.d', 'vfclass.d')
+  print_vec_insts('vfcvt.s.d', 'vfcvt.d.s')
+  print_vec_insts('vfcvt.w.d', 'vfcvt.wu.d')
+  print_vec_insts('vfcvt.d.w', 'vfcvt.d.wu')
+  print_vec_insts('vfcvt.l.d', 'vfcvt.lu.d', 'vfmv.x.d')
+  print_vec_insts('vfcvt.d.l', 'vfcvt.d.lu', 'vfmv.d.x')
+  print_vec_footer()
+  print_vec_header()
+  print_vec_insts('vfmadd.h', 'vfmsub.h')
+  print_vec_insts('vfadd.h', 'vfsub.h', 'vfmul.h', 'vfdiv.h', 'vfsqrt.h')
+  print_vec_insts('vfsgnj.h', 'vfsgnjn.h', 'vfsgnjx.h', 'vfmin.h', 'vfmax.h')
+  print_vec_insts('vfeq.h', 'vflt.h', 'vfle.h', 'vfclass.h')
+  print_vec_insts('vfcvt.s.h', 'vfcvt.h.s')
+  print_vec_insts('vfcvt.w.h', 'vfcvt.wu.h')
+  print_vec_insts('vfcvt.h.w', 'vfcvt.h.wu')
+  print_vec_insts('vfcvt.l.h', 'vfcvt.lu.h', 'vfmv.x.h')
+  print_vec_insts('vfcvt.h.l', 'vfcvt.h.lu', 'vfmv.h.x')
+  print_vec_footer()
+  print_vec_header()
+  print_vec_insts('vfmadd.q', 'vfmsub.q')
+  print_vec_insts('vfadd.q', 'vfsub.q', 'vfmul.q', 'vfdiv.q', 'vfsqrt.q')
+  print_vec_insts('vfsgnj.q', 'vfsgnjn.q', 'vfsgnjx.q', 'vfmin.q', 'vfmax.q')
+  print_vec_insts('vfeq.q', 'vflt.q', 'vfle.q', 'vfclass.q')
+  print_vec_insts('vfcvt.s.q', 'vfcvt.q.s')
+  print_vec_insts('vfcvt.w.q', 'vfcvt.wu.q')
+  print_vec_insts('vfcvt.q.w', 'vfcvt.q.wu')
+  print_vec_insts('vfcvt.l.q', 'vfcvt.lu.q', 'vfmv.x.q')
+  print_vec_insts('vfcvt.q.l', 'vfcvt.q.lu', 'vfmv.q.x')
+  print_vec_footer()
+  print_vec_header()
+  #print_subtitle('RV32V Standard Extension (cont.)', 9)
+  print_vec_insts('vlb', 'vlh', 'vlw', 'vld', 'vlbu', 'vlhu', 'vlwu')
+  print_vec_insts('vlsb', 'vlsh', 'vlsw', 'vlsd', 'vlsbu', 'vlshu', 'vlswu')
+  print_vec_insts('vlxb', 'vlxh', 'vlxw', 'vlxd', 'vlxbu', 'vlxhu', 'vlxwu')
+  print_vec_insts('vlfh', 'vlfs', 'vlfd', 'vlfq')
+  print_vec_insts('vlsfh', 'vlsfs', 'vlsfd', 'vlsfq')
+  print_vec_insts('vlxfh', 'vlxfs', 'vlxfd', 'vlxfq')
+  print_vec_insts('vsb', 'vsh', 'vsw', 'vsd')
+  print_vec_insts('vssb', 'vssh', 'vssw', 'vssd')
+  print_vec_insts('vsxb', 'vsxh', 'vsxw', 'vsxd')
+  print_vec_insts('vsfh', 'vsfs', 'vsfd', 'vsfq')
+  print_vec_insts('vssfh', 'vssfs', 'vssfd', 'vssfq')
+  print_vec_insts('vsxfh', 'vsxfs', 'vsxfd', 'vsxfq')
+  print_vec_insts('vamoswap', 'vamoadd', 'vamoand', 'vamoor', 'vamoxor', 'vamomin', 'vamomax')
+  print_vec_footer()
 
 def print_chisel_insn(name):
   s = "  def %-18s = BitPat(\"b" % name.replace('.', '_').upper()
@@ -1108,6 +1168,8 @@ if sys.argv[1] == '-tex':
   make_latex_table()
 elif sys.argv[1] == '-privtex':
   make_supervisor_latex_table()
+elif sys.argv[1] == '-vecadoc':
+  make_vector_adoc_table()
 elif sys.argv[1] == '-chisel':
   make_chisel()
 elif sys.argv[1] == '-c':