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| author | Andrew Waterman <andrew@sifive.com> | 2019-01-21 22:40:06 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-01-21 22:40:06 -0800 |
| commit | 9d28c9a9a173f197b1983842caae550d60b36706 (patch) | |
| tree | 6f6b5f5a5f8b8bfe222a049cea8b10893433fce7 /opcodes | |
| parent | 1dfd1df36278f89aa3896410dc50b5604087eebd (diff) | |
| download | riscv-opcodes-9d28c9a9a173f197b1983842caae550d60b36706.zip riscv-opcodes-9d28c9a9a173f197b1983842caae550d60b36706.tar.gz riscv-opcodes-9d28c9a9a173f197b1983842caae550d60b36706.tar.bz2 | |
Add tentative hypervisor CSR and instruction encodings
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -128,6 +128,10 @@ csrrwi rd rs1 imm12 14..12=5 6..2=0x1C 1..0=3 csrrsi rd rs1 imm12 14..12=6 6..2=0x1C 1..0=3 csrrci rd rs1 imm12 14..12=7 6..2=0x1C 1..0=3 +# Hypervisor extension +hfence.bvma 11..7=0 rs1 rs2 31..25=0x11 14..12=0 6..2=0x1C 1..0=3 +hfence.gvma 11..7=0 rs1 rs2 31..25=0x51 14..12=0 6..2=0x1C 1..0=3 + # F/D EXTENSIONS fadd.s rd rs1 rs2 31..27=0x00 rm 26..25=0 6..2=0x14 1..0=3 fsub.s rd rs1 rs2 31..27=0x01 rm 26..25=0 6..2=0x14 1..0=3 |