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| author | Colin Schmidt <colins@eecs.berkeley.edu> | 2018-11-01 09:57:09 -0700 |
|---|---|---|
| committer | Colin Schmidt <colins@eecs.berkeley.edu> | 2018-11-01 09:57:09 -0700 |
| commit | fe45aa44cf53dbcda754af51eb426456382dc5f3 (patch) | |
| tree | 919083c049d507aabd92745b4aea545722b44b2d | |
| parent | 7c31df9d840f5ee0c65a380855f6d7c4d3e687da (diff) | |
| download | riscv-opcodes-fe45aa44cf53dbcda754af51eb426456382dc5f3.zip riscv-opcodes-fe45aa44cf53dbcda754af51eb426456382dc5f3.tar.gz riscv-opcodes-fe45aa44cf53dbcda754af51eb426456382dc5f3.tar.bz2 | |
Add vdivu and vremu to match spec
| -rw-r--r-- | opcodes-v | 20 | ||||
| -rwxr-xr-x | parse-opcodes | 2 |
2 files changed, 12 insertions, 10 deletions
@@ -129,21 +129,23 @@ vori m vd vs1 vimm 31..28=6 14=1 6..0=0x57 vandi m vd vs1 vimm 31..28=7 14=1 6..0=0x57 # group 31..28=8 -vadd m vd vs1 vs2 27..25=0 31..28=8 14=1 6..0=0x57 -vsub m vd vs1 vs2 27..25=1 31..28=8 14=1 6..0=0x57 -vdiv m vd vs1 vs2 27..25=2 31..28=8 14=1 6..0=0x57 -vrem m vd vs1 vs2 27..25=3 31..28=8 14=1 6..0=0x57 +vdiv m vd vs1 vs2 27..25=0 31..28=8 14=1 6..0=0x57 +vdivu m vd vs1 vs2 27..25=1 31..28=8 14=1 6..0=0x57 +vrem m vd vs1 vs2 27..25=2 31..28=8 14=1 6..0=0x57 +vremu m vd vs1 vs2 27..25=3 31..28=8 14=1 6..0=0x57 vmul m vd vs1 vs2 27..25=4 31..28=8 14=1 6..0=0x57 vmulh m vd vs1 vs2 27..25=5 31..28=8 14=1 6..0=0x57 vmulhu m vd vs1 vs2 27..25=6 31..28=8 14=1 6..0=0x57 vmulhsu m vd vs1 vs2 27..25=7 31..28=8 14=1 6..0=0x57 # group 31..28=9 -vsl m vd vs1 vs2 27..25=0 31..28=9 14=1 6..0=0x57 -vsrl m vd vs1 vs2 27..25=1 31..28=9 14=1 6..0=0x57 -vsra m vd vs1 vs2 27..25=2 31..28=9 14=1 6..0=0x57 -vor m vd vs1 vs2 27..25=3 31..28=9 14=1 6..0=0x57 -vand m vd vs1 vs2 27..25=4 31..28=9 14=1 6..0=0x57 +vadd m vd vs1 vs2 27..25=0 31..28=9 14=1 6..0=0x57 +vsub m vd vs1 vs2 27..25=1 31..28=9 14=1 6..0=0x57 +vsl m vd vs1 vs2 27..25=2 31..28=9 14=1 6..0=0x57 +vsrl m vd vs1 vs2 27..25=3 31..28=9 14=1 6..0=0x57 +vsra m vd vs1 vs2 27..25=4 31..28=9 14=1 6..0=0x57 +vor m vd vs1 vs2 27..25=5 31..28=9 14=1 6..0=0x57 +vand m vd vs1 vs2 27..25=6 31..28=9 14=1 6..0=0x57 # group 31..28=10 includes instructions that write xd # (and may also read xs1 and/or xs2). diff --git a/parse-opcodes b/parse-opcodes index 2c8c43d..d664580 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -955,8 +955,8 @@ def make_vector_adoc_table(): print_vec_header() print_vec_insts('vadd', 'vsub', 'vsl', 'vsrl', 'vsra', 'vand', 'vor', 'vxor', 'vneg') print_vec_insts('vseq', 'vsne', 'vslt', 'vsge', 'vsltu', 'vsgeu') - print_vec_insts('vdiv', 'vrem', 'vmul', 'vmulh', 'vmulhu', 'vmulhsu') print_vec_insts('vclip', 'vcvt', 'vmpop', 'vmfirst', 'vextract', 'vfextract', 'vinsert', 'vfinsert', 'vmerge', 'vselect', 'vslideup', 'vslidedown', 'vrgather') + print_vec_insts('vdiv', 'vdivu', 'vrem', 'vremu', 'vmul', 'vmulh', 'vmulhu', 'vmulhsu') print_vec_insts('vpopc', 'vredsum', 'vredmax', 'vredmin') print_vec_insts('vaddi', 'vsli', 'vsrli', 'vsrai', 'vclipi', 'vandi', 'vori', 'vxori') print_vec_insts('vconfig') |