[xcc, sim] added rvc insn c.li; misc fixes

3 files changed, 8 insertions, 2 deletions

diff --git a/inst.v b/inst.v
index 191a14c..791b600 100644
--- a/inst.v
+++ b/inst.v
@@ -228,3 +228,4 @@
 `define SETVL      32'b?????_?????_000000000000_001_1110011
 `define VF         32'b00000_?????_????????????_010_1110011
 `define C_ADDI     32'b00000000000000000000000000000000
+`define C_LI       32'b00000000000000000000000000000000
diff --git a/opcodes b/opcodes
index 28e35ed..fa5369b 100644
--- a/opcodes
+++ b/opcodes
@@ -80,7 +80,7 @@ lwu     rd rs1       imm12 9..7=6 6..2=0x00 1..0=3
 
 # NOTE: if you add new store instructions, make sure to modify tc-mips-riscv.c
 # and elfxx-mips.c to detect them.  this is a hack to handle the split immed.
-# just open up those files and search for MATCH_S_W; should be obvious.
+# just open up those files and search for MATCH_SW; should be obvious.
 sb     imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x08 1..0=3
 sh     imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x08 1..0=3
 sw     imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x08 1..0=3
@@ -318,3 +318,4 @@ vf          31..27=0 rs1 imm12    9..7=2     6..2=0x1C 1..0=3
 
 # compressed instructions
 c.addi cimm6 crd5 4..0=0
+c.li   cimm6 crd5 4..0=1
diff --git a/parse-opcodes b/parse-opcodes
index 45d16db..a266d44 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -28,7 +28,6 @@ arglut['crd5'] = (9,5)
 arglut['cimm6'] = (15,10)
 
 typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw,10=b
-typelut[0x00] = 0
 typelut[0x03] = 3
 typelut[0x07] = 3
 typelut[0x13] = 3
@@ -52,6 +51,11 @@ typelut[0x6F] = 1
 typelut[0x77] = 4
 typelut[0x7B] = 4
 
+# XXX RVC
+for i in range(0,3):
+  for j in range(0,8):
+    typelut[j*4+i] = 0
+
 # vector opcodes
 typelut[0x0B] = 4
 typelut[0x0F] = 5