diff options
| author | Colin Schmidt <colins@eecs.berkeley.edu> | 2018-10-10 21:43:59 -0700 |
|---|---|---|
| committer | Colin Schmidt <colins@eecs.berkeley.edu> | 2018-10-10 21:43:59 -0700 |
| commit | f4f8e731b9aa806a9b8595e6f91087cece13af36 (patch) | |
| tree | e74a830c0bffe39470050f5565a6f8c489c08c01 | |
| parent | 174aaae3bd5f7369248149a2db6bad791b83cea7 (diff) | |
| download | riscv-opcodes-f4f8e731b9aa806a9b8595e6f91087cece13af36.zip riscv-opcodes-f4f8e731b9aa806a9b8595e6f91087cece13af36.tar.gz riscv-opcodes-f4f8e731b9aa806a9b8595e6f91087cece13af36.tar.bz2 | |
update load/store encoding for 3 bit imm
| -rw-r--r-- | opcodes-v | 304 | ||||
| -rwxr-xr-x | parse-opcodes | 39 |
2 files changed, 77 insertions, 266 deletions
@@ -1,251 +1,63 @@ # Vector loads & stores # TODO Colin split up -# Overlaid on FP load and store opcode -# 7 integer load types and 4 fp loads * 3 types(unit,stride,index) -# masks are not cleanly encodable so -# 14 encodes predicatable or not -# 14..12=0b000 which would be flb(doesn't exist) -# will be scalar shape vector loads -# 14..12=0b1xx where xx!=00 are the normal v1.t,v1.f -vlb.s vd rs1 24..20=0 vlimm 30..27=0x0 26..25=0 14..12=0 6..0=0x07 -vlb vd rs1 24..20=0 vlimm 30..27=0x0 26..25=0 14..12=5 6..0=0x07 -vlb.f vd rs1 24..20=0 vlimm 30..27=0x0 26..25=0 14..12=6 6..0=0x07 -vlb.t vd rs1 24..20=0 vlimm 30..27=0x0 26..25=0 14..12=7 6..0=0x07 -vlh.s vd rs1 24..20=0 vlimm 30..27=0x1 26..25=0 14..12=0 6..0=0x07 -vlh vd rs1 24..20=0 vlimm 30..27=0x1 26..25=0 14..12=5 6..0=0x07 -vlh.f vd rs1 24..20=0 vlimm 30..27=0x1 26..25=0 14..12=6 6..0=0x07 -vlh.t vd rs1 24..20=0 vlimm 30..27=0x1 26..25=0 14..12=7 6..0=0x07 -vlw.s vd rs1 24..20=0 vlimm 30..27=0x2 26..25=0 14..12=0 6..0=0x07 -vlw vd rs1 24..20=0 vlimm 30..27=0x2 26..25=0 14..12=5 6..0=0x07 -vlw.f vd rs1 24..20=0 vlimm 30..27=0x2 26..25=0 14..12=6 6..0=0x07 -vlw.t vd rs1 24..20=0 vlimm 30..27=0x2 26..25=0 14..12=7 6..0=0x07 -vld.s vd rs1 24..20=0 vlimm 30..27=0x3 26..25=0 14..12=0 6..0=0x07 -vld vd rs1 24..20=0 vlimm 30..27=0x3 26..25=0 14..12=5 6..0=0x07 -vld.f vd rs1 24..20=0 vlimm 30..27=0x3 26..25=0 14..12=6 6..0=0x07 -vld.t vd rs1 24..20=0 vlimm 30..27=0x3 26..25=0 14..12=7 6..0=0x07 -vlbu.s vd rs1 24..20=0 vlimm 30..27=0x4 26..25=0 14..12=0 6..0=0x07 -vlbu vd rs1 24..20=0 vlimm 30..27=0x4 26..25=0 14..12=5 6..0=0x07 -vlbu.f vd rs1 24..20=0 vlimm 30..27=0x4 26..25=0 14..12=6 6..0=0x07 -vlbu.t vd rs1 24..20=0 vlimm 30..27=0x4 26..25=0 14..12=7 6..0=0x07 -vlhu.s vd rs1 24..20=0 vlimm 30..27=0x5 26..25=0 14..12=0 6..0=0x07 -vlhu vd rs1 24..20=0 vlimm 30..27=0x5 26..25=0 14..12=5 6..0=0x07 -vlhu.f vd rs1 24..20=0 vlimm 30..27=0x5 26..25=0 14..12=6 6..0=0x07 -vlhu.t vd rs1 24..20=0 vlimm 30..27=0x5 26..25=0 14..12=7 6..0=0x07 -vlwu.s vd rs1 24..20=0 vlimm 30..27=0x6 26..25=0 14..12=0 6..0=0x07 -vlwu vd rs1 24..20=0 vlimm 30..27=0x6 26..25=0 14..12=5 6..0=0x07 -vlwu.f vd rs1 24..20=0 vlimm 30..27=0x6 26..25=0 14..12=6 6..0=0x07 -vlwu.t vd rs1 24..20=0 vlimm 30..27=0x6 26..25=0 14..12=7 6..0=0x07 - -vlsb.s vd rs1 rs2 vlimm 30..27=0x0 26..25=1 14..12=0 6..0=0x07 -vlsb vd rs1 rs2 vlimm 30..27=0x0 26..25=1 14..12=5 6..0=0x07 -vlsb.f vd rs1 rs2 vlimm 30..27=0x0 26..25=1 14..12=6 6..0=0x07 -vlsb.t vd rs1 rs2 vlimm 30..27=0x0 26..25=1 14..12=7 6..0=0x07 -vlsh.s vd rs1 rs2 vlimm 30..27=0x1 26..25=1 14..12=0 6..0=0x07 -vlsh vd rs1 rs2 vlimm 30..27=0x1 26..25=1 14..12=5 6..0=0x07 -vlsh.f vd rs1 rs2 vlimm 30..27=0x1 26..25=1 14..12=6 6..0=0x07 -vlsh.t vd rs1 rs2 vlimm 30..27=0x1 26..25=1 14..12=7 6..0=0x07 -vlsw.s vd rs1 rs2 vlimm 30..27=0x2 26..25=1 14..12=0 6..0=0x07 -vlsw vd rs1 rs2 vlimm 30..27=0x2 26..25=1 14..12=5 6..0=0x07 -vlsw.f vd rs1 rs2 vlimm 30..27=0x2 26..25=1 14..12=6 6..0=0x07 -vlsw.t vd rs1 rs2 vlimm 30..27=0x2 26..25=1 14..12=7 6..0=0x07 -vlsd.s vd rs1 rs2 vlimm 30..27=0x3 26..25=1 14..12=0 6..0=0x07 -vlsd vd rs1 rs2 vlimm 30..27=0x3 26..25=1 14..12=5 6..0=0x07 -vlsd.f vd rs1 rs2 vlimm 30..27=0x3 26..25=1 14..12=6 6..0=0x07 -vlsd.t vd rs1 rs2 vlimm 30..27=0x3 26..25=1 14..12=7 6..0=0x07 -vlsbu.s vd rs1 rs2 vlimm 30..27=0x4 26..25=1 14..12=0 6..0=0x07 -vlsbu vd rs1 rs2 vlimm 30..27=0x4 26..25=1 14..12=5 6..0=0x07 -vlsbu.f vd rs1 rs2 vlimm 30..27=0x4 26..25=1 14..12=6 6..0=0x07 -vlsbu.t vd rs1 rs2 vlimm 30..27=0x4 26..25=1 14..12=7 6..0=0x07 -vlshu.s vd rs1 rs2 vlimm 30..27=0x5 26..25=1 14..12=0 6..0=0x07 -vlshu vd rs1 rs2 vlimm 30..27=0x5 26..25=1 14..12=5 6..0=0x07 -vlshu.f vd rs1 rs2 vlimm 30..27=0x5 26..25=1 14..12=6 6..0=0x07 -vlshu.t vd rs1 rs2 vlimm 30..27=0x5 26..25=1 14..12=7 6..0=0x07 -vlswu.s vd rs1 rs2 vlimm 30..27=0x6 26..25=1 14..12=0 6..0=0x07 -vlswu vd rs1 rs2 vlimm 30..27=0x6 26..25=1 14..12=5 6..0=0x07 -vlswu.f vd rs1 rs2 vlimm 30..27=0x6 26..25=1 14..12=6 6..0=0x07 -vlswu.t vd rs1 rs2 vlimm 30..27=0x6 26..25=1 14..12=7 6..0=0x07 - -vlxb.s vd rs1 vs2 vlimm 30..27=0x0 26..25=2 14..12=0 6..0=0x07 -vlxb vd rs1 vs2 vlimm 30..27=0x0 26..25=2 14..12=5 6..0=0x07 -vlxb.f vd rs1 vs2 vlimm 30..27=0x0 26..25=2 14..12=6 6..0=0x07 -vlxb.t vd rs1 vs2 vlimm 30..27=0x0 26..25=2 14..12=7 6..0=0x07 -vlxh.s vd rs1 vs2 vlimm 30..27=0x1 26..25=2 14..12=0 6..0=0x07 -vlxh vd rs1 vs2 vlimm 30..27=0x1 26..25=2 14..12=5 6..0=0x07 -vlxh.f vd rs1 vs2 vlimm 30..27=0x1 26..25=2 14..12=6 6..0=0x07 -vlxh.t vd rs1 vs2 vlimm 30..27=0x1 26..25=2 14..12=7 6..0=0x07 -vlxw.s vd rs1 vs2 vlimm 30..27=0x2 26..25=2 14..12=0 6..0=0x07 -vlxw vd rs1 vs2 vlimm 30..27=0x2 26..25=2 14..12=5 6..0=0x07 -vlxw.f vd rs1 vs2 vlimm 30..27=0x2 26..25=2 14..12=6 6..0=0x07 -vlxw.t vd rs1 vs2 vlimm 30..27=0x2 26..25=2 14..12=7 6..0=0x07 -vlxd.s vd rs1 vs2 vlimm 30..27=0x3 26..25=2 14..12=0 6..0=0x07 -vlxd vd rs1 vs2 vlimm 30..27=0x3 26..25=2 14..12=5 6..0=0x07 -vlxd.f vd rs1 vs2 vlimm 30..27=0x3 26..25=2 14..12=6 6..0=0x07 -vlxd.t vd rs1 vs2 vlimm 30..27=0x3 26..25=2 14..12=7 6..0=0x07 -vlxbu.s vd rs1 vs2 vlimm 30..27=0x4 26..25=2 14..12=0 6..0=0x07 -vlxbu vd rs1 vs2 vlimm 30..27=0x4 26..25=2 14..12=5 6..0=0x07 -vlxbu.f vd rs1 vs2 vlimm 30..27=0x4 26..25=2 14..12=6 6..0=0x07 -vlxbu.t vd rs1 vs2 vlimm 30..27=0x4 26..25=2 14..12=7 6..0=0x07 -vlxhu.s vd rs1 vs2 vlimm 30..27=0x5 26..25=2 14..12=0 6..0=0x07 -vlxhu vd rs1 vs2 vlimm 30..27=0x5 26..25=2 14..12=5 6..0=0x07 -vlxhu.f vd rs1 vs2 vlimm 30..27=0x5 26..25=2 14..12=6 6..0=0x07 -vlxhu.t vd rs1 vs2 vlimm 30..27=0x5 26..25=2 14..12=7 6..0=0x07 -vlxwu.s vd rs1 vs2 vlimm 30..27=0x6 26..25=2 14..12=0 6..0=0x07 -vlxwu vd rs1 vs2 vlimm 30..27=0x6 26..25=2 14..12=5 6..0=0x07 -vlxwu.f vd rs1 vs2 vlimm 30..27=0x6 26..25=2 14..12=6 6..0=0x07 -vlxwu.t vd rs1 vs2 vlimm 30..27=0x6 26..25=2 14..12=7 6..0=0x07 - -vlfh.s vd rs1 24..20=0 vlimm 30..27=0x8 26..25=0 14..12=0 6..0=0x07 -vlfh vd rs1 24..20=0 vlimm 30..27=0x8 26..25=0 14..12=5 6..0=0x07 -vlfh.f vd rs1 24..20=0 vlimm 30..27=0x8 26..25=0 14..12=6 6..0=0x07 -vlfh.t vd rs1 24..20=0 vlimm 30..27=0x8 26..25=0 14..12=7 6..0=0x07 -vlfs.s vd rs1 24..20=0 vlimm 30..27=0x9 26..25=0 14..12=0 6..0=0x07 -vlfs vd rs1 24..20=0 vlimm 30..27=0x9 26..25=0 14..12=5 6..0=0x07 -vlfs.f vd rs1 24..20=0 vlimm 30..27=0x9 26..25=0 14..12=6 6..0=0x07 -vlfs.t vd rs1 24..20=0 vlimm 30..27=0x9 26..25=0 14..12=7 6..0=0x07 -vlfd.s vd rs1 24..20=0 vlimm 30..27=0xa 26..25=0 14..12=0 6..0=0x07 -vlfd vd rs1 24..20=0 vlimm 30..27=0xa 26..25=0 14..12=5 6..0=0x07 -vlfd.f vd rs1 24..20=0 vlimm 30..27=0xa 26..25=0 14..12=6 6..0=0x07 -vlfd.t vd rs1 24..20=0 vlimm 30..27=0xa 26..25=0 14..12=7 6..0=0x07 -vlfq.s vd rs1 24..20=0 vlimm 30..27=0xb 26..25=0 14..12=0 6..0=0x07 -vlfq vd rs1 24..20=0 vlimm 30..27=0xb 26..25=0 14..12=5 6..0=0x07 -vlfq.f vd rs1 24..20=0 vlimm 30..27=0xb 26..25=0 14..12=6 6..0=0x07 -vlfq.t vd rs1 24..20=0 vlimm 30..27=0xb 26..25=0 14..12=7 6..0=0x07 - -vlsfh.s vd rs1 rs2 vlimm 30..27=0x8 26..25=1 14..12=0 6..0=0x07 -vlsfh vd rs1 rs2 vlimm 30..27=0x8 26..25=1 14..12=5 6..0=0x07 -vlsfh.f vd rs1 rs2 vlimm 30..27=0x8 26..25=1 14..12=6 6..0=0x07 -vlsfh.t vd rs1 rs2 vlimm 30..27=0x8 26..25=1 14..12=7 6..0=0x07 -vlsfs.s vd rs1 rs2 vlimm 30..27=0x9 26..25=1 14..12=0 6..0=0x07 -vlsfs vd rs1 rs2 vlimm 30..27=0x9 26..25=1 14..12=5 6..0=0x07 -vlsfs.f vd rs1 rs2 vlimm 30..27=0x9 26..25=1 14..12=6 6..0=0x07 -vlsfs.t vd rs1 rs2 vlimm 30..27=0x9 26..25=1 14..12=7 6..0=0x07 -vlsfd.s vd rs1 rs2 vlimm 30..27=0xa 26..25=1 14..12=0 6..0=0x07 -vlsfd vd rs1 rs2 vlimm 30..27=0xa 26..25=1 14..12=5 6..0=0x07 -vlsfd.f vd rs1 rs2 vlimm 30..27=0xa 26..25=1 14..12=6 6..0=0x07 -vlsfd.t vd rs1 rs2 vlimm 30..27=0xa 26..25=1 14..12=7 6..0=0x07 -vlsfq.s vd rs1 rs2 vlimm 30..27=0xb 26..25=1 14..12=0 6..0=0x07 -vlsfq vd rs1 rs2 vlimm 30..27=0xb 26..25=1 14..12=5 6..0=0x07 -vlsfq.f vd rs1 rs2 vlimm 30..27=0xb 26..25=1 14..12=6 6..0=0x07 -vlsfq.t vd rs1 rs2 vlimm 30..27=0xb 26..25=1 14..12=7 6..0=0x07 - -vlxfh.s vd rs1 vs2 vlimm 30..27=0x8 26..25=2 14..12=0 6..0=0x07 -vlxfh vd rs1 vs2 vlimm 30..27=0x8 26..25=2 14..12=5 6..0=0x07 -vlxfh.f vd rs1 vs2 vlimm 30..27=0x8 26..25=2 14..12=6 6..0=0x07 -vlxfh.t vd rs1 vs2 vlimm 30..27=0x8 26..25=2 14..12=7 6..0=0x07 -vlxfs.s vd rs1 vs2 vlimm 30..27=0x9 26..25=2 14..12=0 6..0=0x07 -vlxfs vd rs1 vs2 vlimm 30..27=0x9 26..25=2 14..12=5 6..0=0x07 -vlxfs.f vd rs1 vs2 vlimm 30..27=0x9 26..25=2 14..12=6 6..0=0x07 -vlxfs.t vd rs1 vs2 vlimm 30..27=0x9 26..25=2 14..12=7 6..0=0x07 -vlxfd.s vd rs1 vs2 vlimm 30..27=0xa 26..25=2 14..12=0 6..0=0x07 -vlxfd vd rs1 vs2 vlimm 30..27=0xa 26..25=2 14..12=5 6..0=0x07 -vlxfd.f vd rs1 vs2 vlimm 30..27=0xa 26..25=2 14..12=6 6..0=0x07 -vlxfd.t vd rs1 vs2 vlimm 30..27=0xa 26..25=2 14..12=7 6..0=0x07 -vlxfq.s vd rs1 vs2 vlimm 30..27=0xb 26..25=2 14..12=0 6..0=0x07 -vlxfq vd rs1 vs2 vlimm 30..27=0xb 26..25=2 14..12=5 6..0=0x07 -vlxfq.f vd rs1 vs2 vlimm 30..27=0xb 26..25=2 14..12=6 6..0=0x07 -vlxfq.t vd rs1 vs2 vlimm 30..27=0xb 26..25=2 14..12=7 6..0=0x07 - -vsb.s vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=0 14..12=0 6..0=0x27 -vsb vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=0 14..12=5 6..0=0x27 -vsb.f vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=0 14..12=6 6..0=0x27 -vsb.t vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=0 14..12=7 6..0=0x27 -vsh.s vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=0 14..12=0 6..0=0x27 -vsh vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=0 14..12=5 6..0=0x27 -vsh.f vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=0 14..12=6 6..0=0x27 -vsh.t vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=0 14..12=7 6..0=0x27 -vsw.s vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=0 14..12=0 6..0=0x27 -vsw vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=0 14..12=5 6..0=0x27 -vsw.f vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=0 14..12=6 6..0=0x27 -vsw.t vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=0 14..12=7 6..0=0x27 -vsd.s vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=0 14..12=0 6..0=0x27 -vsd vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=0 14..12=5 6..0=0x27 -vsd.f vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=0 14..12=6 6..0=0x27 -vsd.t vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=0 14..12=7 6..0=0x27 - -vssb.s vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=1 14..12=0 6..0=0x27 -vssb vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=1 14..12=5 6..0=0x27 -vssb.f vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=1 14..12=6 6..0=0x27 -vssb.t vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=1 14..12=7 6..0=0x27 -vssh.s vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=1 14..12=0 6..0=0x27 -vssh vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=1 14..12=5 6..0=0x27 -vssh.f vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=1 14..12=6 6..0=0x27 -vssh.t vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=1 14..12=7 6..0=0x27 -vssw.s vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=1 14..12=0 6..0=0x27 -vssw vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=1 14..12=5 6..0=0x27 -vssw.f vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=1 14..12=6 6..0=0x27 -vssw.t vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=1 14..12=7 6..0=0x27 -vssd.s vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=1 14..12=0 6..0=0x27 -vssd vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=1 14..12=5 6..0=0x27 -vssd.f vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=1 14..12=6 6..0=0x27 -vssd.t vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=1 14..12=7 6..0=0x27 - -vsxb.s vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=2 14..12=0 6..0=0x27 -vsxb vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=2 14..12=5 6..0=0x27 -vsxb.f vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=2 14..12=6 6..0=0x27 -vsxb.t vs3 rs1 24..20=0 vsimm 9..7=0x0 26..25=2 14..12=7 6..0=0x27 -vsxh.s vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=2 14..12=0 6..0=0x27 -vsxh vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=2 14..12=5 6..0=0x27 -vsxh.f vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=2 14..12=6 6..0=0x27 -vsxh.t vs3 rs1 24..20=0 vsimm 9..7=0x1 26..25=2 14..12=7 6..0=0x27 -vsxw.s vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=2 14..12=0 6..0=0x27 -vsxw vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=2 14..12=5 6..0=0x27 -vsxw.f vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=2 14..12=6 6..0=0x27 -vsxw.t vs3 rs1 24..20=0 vsimm 9..7=0x2 26..25=2 14..12=7 6..0=0x27 -vsxd.s vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=2 14..12=0 6..0=0x27 -vsxd vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=2 14..12=5 6..0=0x27 -vsxd.f vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=2 14..12=6 6..0=0x27 -vsxd.t vs3 rs1 24..20=0 vsimm 9..7=0x3 26..25=2 14..12=7 6..0=0x27 - -vsfh.s vs3 rs1 24..20=0 vsimm 9..7=0x4 26..25=0 14..12=0 6..0=0x27 -vsfh vs3 rs1 24..20=0 vsimm 9..7=0x4 26..25=0 14..12=5 6..0=0x27 -vsfh.f vs3 rs1 24..20=0 vsimm 9..7=0x4 26..25=0 14..12=6 6..0=0x27 -vsfh.t vs3 rs1 24..20=0 vsimm 9..7=0x4 26..25=0 14..12=7 6..0=0x27 -vsfs.s vs3 rs1 24..20=0 vsimm 9..7=0x5 26..25=0 14..12=0 6..0=0x27 -vsfs vs3 rs1 24..20=0 vsimm 9..7=0x5 26..25=0 14..12=5 6..0=0x27 -vsfs.f vs3 rs1 24..20=0 vsimm 9..7=0x5 26..25=0 14..12=6 6..0=0x27 -vsfs.t vs3 rs1 24..20=0 vsimm 9..7=0x5 26..25=0 14..12=7 6..0=0x27 -vsfd.s vs3 rs1 24..20=0 vsimm 9..7=0x6 26..25=0 14..12=0 6..0=0x27 -vsfd vs3 rs1 24..20=0 vsimm 9..7=0x6 26..25=0 14..12=5 6..0=0x27 -vsfd.f vs3 rs1 24..20=0 vsimm 9..7=0x6 26..25=0 14..12=6 6..0=0x27 -vsfd.t vs3 rs1 24..20=0 vsimm 9..7=0x6 26..25=0 14..12=7 6..0=0x27 -vsfq.s vs3 rs1 24..20=0 vsimm 9..7=0x7 26..25=0 14..12=0 6..0=0x27 -vsfq vs3 rs1 24..20=0 vsimm 9..7=0x7 26..25=0 14..12=5 6..0=0x27 -vsfq.f vs3 rs1 24..20=0 vsimm 9..7=0x7 26..25=0 14..12=6 6..0=0x27 -vsfq.t vs3 rs1 24..20=0 vsimm 9..7=0x7 26..25=0 14..12=7 6..0=0x27 - -vssfh.s vs3 rs1 rs2 vsimm 9..7=0x4 26..25=1 14..12=0 6..0=0x27 -vssfh vs3 rs1 rs2 vsimm 9..7=0x4 26..25=1 14..12=5 6..0=0x27 -vssfh.f vs3 rs1 rs2 vsimm 9..7=0x4 26..25=1 14..12=6 6..0=0x27 -vssfh.t vs3 rs1 rs2 vsimm 9..7=0x4 26..25=1 14..12=7 6..0=0x27 -vssfs.s vs3 rs1 rs2 vsimm 9..7=0x5 26..25=1 14..12=0 6..0=0x27 -vssfs vs3 rs1 rs2 vsimm 9..7=0x5 26..25=1 14..12=5 6..0=0x27 -vssfs.f vs3 rs1 rs2 vsimm 9..7=0x5 26..25=1 14..12=6 6..0=0x27 -vssfs.t vs3 rs1 rs2 vsimm 9..7=0x5 26..25=1 14..12=7 6..0=0x27 -vssfd.s vs3 rs1 rs2 vsimm 9..7=0x6 26..25=1 14..12=0 6..0=0x27 -vssfd vs3 rs1 rs2 vsimm 9..7=0x6 26..25=1 14..12=5 6..0=0x27 -vssfd.f vs3 rs1 rs2 vsimm 9..7=0x6 26..25=1 14..12=6 6..0=0x27 -vssfd.t vs3 rs1 rs2 vsimm 9..7=0x6 26..25=1 14..12=7 6..0=0x27 -vssfq.s vs3 rs1 rs2 vsimm 9..7=0x7 26..25=1 14..12=0 6..0=0x27 -vssfq vs3 rs1 rs2 vsimm 9..7=0x7 26..25=1 14..12=5 6..0=0x27 -vssfq.f vs3 rs1 rs2 vsimm 9..7=0x7 26..25=1 14..12=6 6..0=0x27 -vssfq.t vs3 rs1 rs2 vsimm 9..7=0x7 26..25=1 14..12=7 6..0=0x27 - -vsxfh.s vs3 rs1 vs2 vsimm 9..7=0x4 26..25=2 14..12=0 6..0=0x27 -vsxfh vs3 rs1 vs2 vsimm 9..7=0x4 26..25=2 14..12=5 6..0=0x27 -vsxfh.f vs3 rs1 vs2 vsimm 9..7=0x4 26..25=2 14..12=6 6..0=0x27 -vsxfh.t vs3 rs1 vs2 vsimm 9..7=0x4 26..25=2 14..12=7 6..0=0x27 -vsxfs.s vs3 rs1 vs2 vsimm 9..7=0x5 26..25=2 14..12=0 6..0=0x27 -vsxfs vs3 rs1 vs2 vsimm 9..7=0x5 26..25=2 14..12=5 6..0=0x27 -vsxfs.f vs3 rs1 vs2 vsimm 9..7=0x5 26..25=2 14..12=6 6..0=0x27 -vsxfs.t vs3 rs1 vs2 vsimm 9..7=0x5 26..25=2 14..12=7 6..0=0x27 -vsxfd.s vs3 rs1 vs2 vsimm 9..7=0x6 26..25=2 14..12=0 6..0=0x27 -vsxfd vs3 rs1 vs2 vsimm 9..7=0x6 26..25=2 14..12=5 6..0=0x27 -vsxfd.f vs3 rs1 vs2 vsimm 9..7=0x6 26..25=2 14..12=6 6..0=0x27 -vsxfd.t vs3 rs1 vs2 vsimm 9..7=0x6 26..25=2 14..12=7 6..0=0x27 -vsxfq.s vs3 rs1 vs2 vsimm 9..7=0x7 26..25=2 14..12=0 6..0=0x27 -vsxfq vs3 rs1 vs2 vsimm 9..7=0x7 26..25=2 14..12=5 6..0=0x27 -vsxfq.f vs3 rs1 vs2 vsimm 9..7=0x7 26..25=2 14..12=6 6..0=0x27 -vsxfq.t vs3 rs1 vs2 vsimm 9..7=0x7 26..25=2 14..12=7 6..0=0x27 +# +# Use 14..12 as the 4 sizes of memory ops (B, H, W, D) +# 14..12=0 Vector Byte +# 5 Vector Half +# 6 Vector Word +# 7 Vector DoubleWord +# Use 26..25 for mask field +# Use bit 27 for strided or indexed (strided with x0 is unit stride) +# Use 28 for signed/unsigned (load fp lives in store opcode) +# 31..29 for immeadiate +# +# For stores bit 28 and 27 move to 8 and 7 and bit 8 means int or fp +# +@vlb vd rs1 24..20=0 vlimm mm 28=0 27=0 14..12=0 6..0=0x07 +@vlh vd rs1 24..20=0 vlimm mm 28=0 27=0 14..12=5 6..0=0x07 +@vlw vd rs1 24..20=0 vlimm mm 28=0 27=0 14..12=6 6..0=0x07 +@vld vd rs1 24..20=0 vlimm mm 28=0 27=0 14..12=7 6..0=0x07 +@vlbu vd rs1 24..20=0 vlimm mm 28=1 27=0 14..12=0 6..0=0x07 +@vlhu vd rs1 24..20=0 vlimm mm 28=1 27=0 14..12=5 6..0=0x07 +@vlwu vd rs1 24..20=0 vlimm mm 28=1 27=0 14..12=6 6..0=0x07 +vlsb vd rs1 rs2 vlimm mm 28=0 27=0 14..12=0 6..0=0x07 +vlsh vd rs1 rs2 vlimm mm 28=0 27=0 14..12=5 6..0=0x07 +vlsw vd rs1 rs2 vlimm mm 28=0 27=0 14..12=6 6..0=0x07 +vlsd vd rs1 rs2 vlimm mm 28=0 27=0 14..12=7 6..0=0x07 +vlsbu vd rs1 rs2 vlimm mm 28=1 27=0 14..12=0 6..0=0x07 +vlshu vd rs1 rs2 vlimm mm 28=1 27=0 14..12=5 6..0=0x07 +vlswu vd rs1 rs2 vlimm mm 28=1 27=0 14..12=6 6..0=0x07 +vlxb vd rs1 vs2 vlimm mm 28=0 27=1 14..12=0 6..0=0x07 +vlxh vd rs1 vs2 vlimm mm 28=0 27=1 14..12=5 6..0=0x07 +vlxw vd rs1 vs2 vlimm mm 28=0 27=1 14..12=6 6..0=0x07 +vlxd vd rs1 vs2 vlimm mm 28=0 27=1 14..12=7 6..0=0x07 +vlxbu vd rs1 vs2 vlimm mm 28=1 27=1 14..12=0 6..0=0x07 +vlxhu vd rs1 vs2 vlimm mm 28=1 27=1 14..12=5 6..0=0x07 +vlxwu vd rs1 vs2 vlimm mm 28=1 27=1 14..12=6 6..0=0x07 + +# FP loads use the store opcode +@vlfh vs3 rs1 24..20=0 vsimm mm 8=1 7=0 14..12=5 6..0=0x27 +@vlfs vs3 rs1 24..20=0 vsimm mm 8=1 7=0 14..12=6 6..0=0x27 +@vlfd vs3 rs1 24..20=0 vsimm mm 8=1 7=0 14..12=7 6..0=0x27 +vlsfh vs3 rs1 rs2 vsimm mm 8=1 7=0 14..12=5 6..0=0x27 +vlsfs vs3 rs1 rs2 vsimm mm 8=1 7=0 14..12=6 6..0=0x27 +vlsfd vs3 rs1 rs2 vsimm mm 8=1 7=0 14..12=7 6..0=0x27 +vlxfh vs3 rs1 vs2 vsimm mm 8=1 7=1 14..12=5 6..0=0x27 +vlxfs vs3 rs1 vs2 vsimm mm 8=1 7=1 14..12=6 6..0=0x27 +vlxfd vs3 rs1 vs2 vsimm mm 8=1 7=1 14..12=7 6..0=0x27 + +@vsb vs3 rs1 24..20=0 vsimm mm 8=0 7=0 14..12=0 6..0=0x27 +@vsh vs3 rs1 24..20=0 vsimm mm 8=0 7=0 14..12=5 6..0=0x27 +@vsw vs3 rs1 24..20=0 vsimm mm 8=0 7=0 14..12=6 6..0=0x27 +@vsd vs3 rs1 24..20=0 vsimm mm 8=0 7=0 14..12=7 6..0=0x27 +vssb vs3 rs1 rs2 vsimm mm 8=0 7=0 14..12=0 6..0=0x27 +vssh vs3 rs1 rs2 vsimm mm 8=0 7=0 14..12=5 6..0=0x27 +vssw vs3 rs1 rs2 vsimm mm 8=0 7=0 14..12=6 6..0=0x27 +vssd vs3 rs1 rs2 vsimm mm 8=0 7=0 14..12=7 6..0=0x27 +vsxb vs3 rs1 rs2 vsimm mm 8=0 7=1 14..12=0 6..0=0x27 +vsxh vs3 rs1 rs2 vsimm mm 8=0 7=1 14..12=5 6..0=0x27 +vsxw vs3 rs1 rs2 vsimm mm 8=0 7=1 14..12=6 6..0=0x27 +vsxd vs3 rs1 rs2 vsimm mm 8=0 7=1 14..12=7 6..0=0x27 # Vector AMOs vamoswap m vd vs3 vs2 19..15=0x01 26..25=3 14=1 6..0=0x27 diff --git a/parse-opcodes b/parse-opcodes index 1617ec2..c2f3d49 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -35,9 +35,10 @@ arglut['vs1'] = (19,15) arglut['vs2'] = (24,20) arglut['vs3'] = (31,27) arglut['m'] = (13,12) +arglut['mm'] = (26,25) arglut['vimm'] = (27,20) -arglut['vlimm'] = (31,31) -arglut['vsimm'] = (11,10) +arglut['vlimm'] = (31,29) +arglut['vsimm'] = (11,9) causes = [ (0x00, 'misaligned fetch'), @@ -633,34 +634,35 @@ def print_vs_type(name,match,arguments): print """3+|%s|%s|%s|%s|%s|%s|%s|%s|%s|%s""" % \ ( \ 'vlimm' in arguments and 'imm[0]' or str_arg('vs3','',match,arguments), \ - binary(yank(match,25,2),2), \ + str_arg('mm','m',match,arguments), \ str_arg('rs2' in arguments and 'rs2' or 'vs2','',match,arguments), \ str_arg('rs1' in arguments and 'rs1' or 'vs1','',match,arguments), \ binary(yank(match,14,1),1), \ - str_arg('m','',match,arguments), \ - 'vsimm' in arguments and 'imm[1:0]' or str_arg('vd','',match,arguments), \ - binary(yank(match,7,3),3), \ + binary(yank(match,12,2),2), \ + 'vsimm' in arguments and 'imm[2:0]' or str_arg('vd','',match,arguments), \ + binary(yank(match,7,2),2), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_vl_type(name,match,arguments): - print """|%s 2+|%s|%s|%s|%s|%s|%s 2+|%s|%s|%s""" % \ + print """|%s|%s|%s|%s|%s|%s|%s|%s 2+|%s|%s|%s""" % \ ( \ - 'vlimm' in arguments and 'imm[0]' or str_arg('vs3','',match,arguments), \ - binary(yank(match,27,4),4), \ - binary(yank(match,25,2),2), \ + 'vlimm' in arguments and 'imm[2:0]' or str_arg('vs3','',match,arguments), \ + binary(yank(match,28,1),1), \ + binary(yank(match,27,1),1), \ + str_arg('mm','m',match,arguments), \ str_arg('rs2' in arguments and 'rs2' or 'vs2','',match,arguments), \ str_arg('rs1' in arguments and 'rs1' or 'vs1','',match,arguments), \ binary(yank(match,14,1),1), \ - str_arg('m','',match,arguments), \ + binary(yank(match,12,2),2), \ 'vsimm' in arguments and 'imm[1:0]' or str_arg('vd','',match,arguments), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_vr4_type(name,match,arguments): - print """ 2+|%s 2+|%s|%s|%s|%s|%s 2+|%s|%s|%s""" % \ + print """ 3+|%s|%s|%s|%s|%s|%s 2+|%s|%s|%s""" % \ ( \ str_arg('rs3' in arguments and 'rs3' or 'vs3','',match,arguments), \ binary(yank(match,25,2),2), \ @@ -796,9 +798,9 @@ def print_vec_subtitle(title): def print_vec_header(): print """ .Vector Table -[width="100%",cols="1,3,1,2,5,5,1,2,2,3,7,10"] +[width="100%",cols="^3,^1,^1,^3,^4,^4,^1,^3,^3,^3,^7,<10"] |======================== -|31 |30 28 |27 |26 25 |24 20 |19 15 |14 |13 12 |11 10 |9 7 |6 0 |Opcode +|31 29 |28 |27 |26 25 |24 20 |19 15 |14 |13 12 |11 9 |8 7 |6 0 |Opcode """ def print_vec_footer(): @@ -1006,15 +1008,12 @@ def make_vector_adoc_table(): print_vec_insts('vlb', 'vlh', 'vlw', 'vld', 'vlbu', 'vlhu', 'vlwu') print_vec_insts('vlsb', 'vlsh', 'vlsw', 'vlsd', 'vlsbu', 'vlshu', 'vlswu') print_vec_insts('vlxb', 'vlxh', 'vlxw', 'vlxd', 'vlxbu', 'vlxhu', 'vlxwu') - print_vec_insts('vlfh', 'vlfs', 'vlfd', 'vlfq') - print_vec_insts('vlsfh', 'vlsfs', 'vlsfd', 'vlsfq') - print_vec_insts('vlxfh', 'vlxfs', 'vlxfd', 'vlxfq') + print_vec_insts('vlfh', 'vlfs', 'vlfd') + print_vec_insts('vlsfh', 'vlsfs', 'vlsfd') + print_vec_insts('vlxfh', 'vlxfs', 'vlxfd') print_vec_insts('vsb', 'vsh', 'vsw', 'vsd') print_vec_insts('vssb', 'vssh', 'vssw', 'vssd') print_vec_insts('vsxb', 'vsxh', 'vsxw', 'vsxd') - print_vec_insts('vsfh', 'vsfs', 'vsfd', 'vsfq') - print_vec_insts('vssfh', 'vssfs', 'vssfd', 'vssfq') - print_vec_insts('vsxfh', 'vsxfs', 'vsxfd', 'vsxfq') print_vec_insts('vamoswap', 'vamoadd', 'vamoand', 'vamoor', 'vamoxor', 'vamomin', 'vamomax') print_vec_footer() |