diff options
| author | Colin Schmidt <colins@berkeley.edu> | 2018-12-21 09:28:09 +0530 |
|---|---|---|
| committer | Colin Schmidt <colins@berkeley.edu> | 2018-12-21 09:28:09 +0530 |
| commit | daf66b12224030a7eb9210bba53151d9df5f9ee9 (patch) | |
| tree | c547d7dea40d4f0333c95d76541a9eaf126605f9 | |
| parent | 5989d0d743185b54e60e98a23390c01624826fa4 (diff) | |
| download | riscv-opcodes-daf66b12224030a7eb9210bba53151d9df5f9ee9.zip riscv-opcodes-daf66b12224030a7eb9210bba53151d9df5f9ee9.tar.gz riscv-opcodes-daf66b12224030a7eb9210bba53151d9df5f9ee9.tar.bz2 | |
separate load/store encodings
| -rw-r--r-- | opcodes-v | 182 | ||||
| -rwxr-xr-x | parse-opcodes | 40 |
2 files changed, 119 insertions, 103 deletions
@@ -1,95 +1,95 @@ # Vector loads & stores -vlb.v vm vd rs1 29=1 28..27=0 vmimm vimm 14..12=0 6..0=0x07 -vlh.v vm vd rs1 29=1 28..27=0 vmimm vimm 14..12=5 6..0=0x07 -vlw.v vm vd rs1 29=1 28..27=0 vmimm vimm 14..12=6 6..0=0x07 -vle.v vm vd rs1 29=1 28..27=0 vmimm vimm 14..12=7 6..0=0x07 -vlbu.v vm vd rs1 29=0 28..27=0 vmimm vimm 14..12=0 6..0=0x07 -vlhu.v vm vd rs1 29=0 28..27=0 vmimm vimm 14..12=5 6..0=0x07 -vlwu.v vm vd rs1 29=0 28..27=0 vmimm vimm 14..12=6 6..0=0x07 -vleu.v vm vd rs1 29=0 28..27=0 vmimm vimm 14..12=7 6..0=0x07 - -vlsb.v vm vd rs1 29=1 28..27=2 vmimm rs2 14..12=0 6..0=0x07 -vlsh.v vm vd rs1 29=1 28..27=2 vmimm rs2 14..12=5 6..0=0x07 -vlsw.v vm vd rs1 29=1 28..27=2 vmimm rs2 14..12=6 6..0=0x07 -vlse.v vm vd rs1 29=1 28..27=2 vmimm rs2 14..12=7 6..0=0x07 -vlsbu.v vm vd rs1 29=0 28..27=2 vmimm rs2 14..12=0 6..0=0x07 -vlshu.v vm vd rs1 29=0 28..27=2 vmimm rs2 14..12=5 6..0=0x07 -vlswu.v vm vd rs1 29=0 28..27=2 vmimm rs2 14..12=6 6..0=0x07 -vlseu.v vm vd rs1 29=0 28..27=2 vmimm rs2 14..12=7 6..0=0x07 - -vlxb.v vm vd rs1 29=1 28..27=3 vmimm vs2 14..12=0 6..0=0x07 -vlxh.v vm vd rs1 29=1 28..27=3 vmimm vs2 14..12=5 6..0=0x07 -vlxw.v vm vd rs1 29=1 28..27=3 vmimm vs2 14..12=6 6..0=0x07 -vlxe.v vm vd rs1 29=1 28..27=3 vmimm vs2 14..12=7 6..0=0x07 -vlxbu.v vm vd rs1 29=0 28..27=3 vmimm vs2 14..12=0 6..0=0x07 -vlxhu.v vm vd rs1 29=0 28..27=3 vmimm vs2 14..12=5 6..0=0x07 -vlxwu.v vm vd rs1 29=0 28..27=3 vmimm vs2 14..12=6 6..0=0x07 -vlxeu.v vm vd rs1 29=0 28..27=3 vmimm vs2 14..12=7 6..0=0x07 - -@vlb.s 26..25=2 vd rs1 29=1 28..27=0 vmimm vimm 14..12=0 6..0=0x07 -@vlh.s 26..25=2 vd rs1 29=1 28..27=0 vmimm vimm 14..12=5 6..0=0x07 -@vlw.s 26..25=2 vd rs1 29=1 28..27=0 vmimm vimm 14..12=6 6..0=0x07 -@vle.s 26..25=2 vd rs1 29=1 28..27=0 vmimm vimm 14..12=7 6..0=0x07 -@vlbu.s 26..25=2 vd rs1 29=0 28..27=0 vmimm vimm 14..12=0 6..0=0x07 -@vlhu.s 26..25=2 vd rs1 29=0 28..27=0 vmimm vimm 14..12=5 6..0=0x07 -@vlwu.s 26..25=2 vd rs1 29=0 28..27=0 vmimm vimm 14..12=6 6..0=0x07 -@vleu.s 26..25=2 vd rs1 29=0 28..27=0 vmimm vimm 14..12=7 6..0=0x07 - -@vlsb.s 26..25=2 vd rs1 29=1 28..27=2 vmimm rs2 14..12=0 6..0=0x07 -@vlsh.s 26..25=2 vd rs1 29=1 28..27=2 vmimm rs2 14..12=5 6..0=0x07 -@vlsw.s 26..25=2 vd rs1 29=1 28..27=2 vmimm rs2 14..12=6 6..0=0x07 -@vlse.s 26..25=2 vd rs1 29=1 28..27=2 vmimm rs2 14..12=7 6..0=0x07 -@vlsbu.s 26..25=2 vd rs1 29=0 28..27=2 vmimm rs2 14..12=0 6..0=0x07 -@vlshu.s 26..25=2 vd rs1 29=0 28..27=2 vmimm rs2 14..12=5 6..0=0x07 -@vlswu.s 26..25=2 vd rs1 29=0 28..27=2 vmimm rs2 14..12=6 6..0=0x07 -@vlseu.s 26..25=2 vd rs1 29=0 28..27=2 vmimm rs2 14..12=7 6..0=0x07 - -@vlxb.s 26..25=2 vd rs1 29=1 28..27=3 vmimm vs2 14..12=0 6..0=0x07 -@vlxh.s 26..25=2 vd rs1 29=1 28..27=3 vmimm vs2 14..12=5 6..0=0x07 -@vlxw.s 26..25=2 vd rs1 29=1 28..27=3 vmimm vs2 14..12=6 6..0=0x07 -@vlxe.s 26..25=2 vd rs1 29=1 28..27=3 vmimm vs2 14..12=7 6..0=0x07 -@vlxbu.s 26..25=2 vd rs1 29=0 28..27=3 vmimm vs2 14..12=0 6..0=0x07 -@vlxhu.s 26..25=2 vd rs1 29=0 28..27=3 vmimm vs2 14..12=5 6..0=0x07 -@vlxwu.s 26..25=2 vd rs1 29=0 28..27=3 vmimm vs2 14..12=6 6..0=0x07 -@vlxeu.s 26..25=2 vd rs1 29=0 28..27=3 vmimm vs2 14..12=7 6..0=0x07 - -vsb.v vm vd rs1 29=0 28..27=0 vmimm vimm 14..12=0 6..0=0x27 -vsh.v vm vd rs1 29=0 28..27=0 vmimm vimm 14..12=5 6..0=0x27 -vsw.v vm vd rs1 29=0 28..27=0 vmimm vimm 14..12=6 6..0=0x27 -vse.v vm vd rs1 29=0 28..27=0 vmimm vimm 14..12=7 6..0=0x27 - -vssb.v vm vd rs1 29=0 28..27=2 vmimm rs2 14..12=0 6..0=0x27 -vssh.v vm vd rs1 29=0 28..27=2 vmimm rs2 14..12=5 6..0=0x27 -vssw.v vm vd rs1 29=0 28..27=2 vmimm rs2 14..12=6 6..0=0x27 -vsse.v vm vd rs1 29=0 28..27=2 vmimm rs2 14..12=7 6..0=0x27 - -vsxb.v vm vd rs1 29=0 28..27=3 vmimm vs2 14..12=0 6..0=0x27 -vsxh.v vm vd rs1 29=0 28..27=3 vmimm vs2 14..12=5 6..0=0x27 -vsxw.v vm vd rs1 29=0 28..27=3 vmimm vs2 14..12=6 6..0=0x27 -vsxe.v vm vd rs1 29=0 28..27=3 vmimm vs2 14..12=7 6..0=0x27 -vsuxb.v vm vd rs1 29=1 28..27=3 vmimm vs2 14..12=0 6..0=0x27 -vsuxh.v vm vd rs1 29=1 28..27=3 vmimm vs2 14..12=5 6..0=0x27 -vsuxw.v vm vd rs1 29=1 28..27=3 vmimm vs2 14..12=6 6..0=0x27 -vsuxe.v vm vd rs1 29=1 28..27=3 vmimm vs2 14..12=7 6..0=0x27 - -@vsb.s 26..25=2 vd rs1 29=0 28..27=0 vmimm vimm 14..12=0 6..0=0x27 -@vsh.s 26..25=2 vd rs1 29=0 28..27=0 vmimm vimm 14..12=5 6..0=0x27 -@vsw.s 26..25=2 vd rs1 29=0 28..27=0 vmimm vimm 14..12=6 6..0=0x27 -@vse.s 26..25=2 vd rs1 29=0 28..27=0 vmimm vimm 14..12=7 6..0=0x27 - -@vssb.s 26..25=2 vd rs1 29=0 28..27=2 vmimm rs2 14..12=0 6..0=0x27 -@vssh.s 26..25=2 vd rs1 29=0 28..27=2 vmimm rs2 14..12=5 6..0=0x27 -@vssw.s 26..25=2 vd rs1 29=0 28..27=2 vmimm rs2 14..12=6 6..0=0x27 -@vsse.s 26..25=2 vd rs1 29=0 28..27=2 vmimm rs2 14..12=7 6..0=0x27 - -@vsxb.s 26..25=2 vd rs1 29=0 28..27=3 vmimm vs2 14..12=0 6..0=0x27 -@vsxh.s 26..25=2 vd rs1 29=0 28..27=3 vmimm vs2 14..12=5 6..0=0x27 -@vsxw.s 26..25=2 vd rs1 29=0 28..27=3 vmimm vs2 14..12=6 6..0=0x27 -@vsxe.s 26..25=2 vd rs1 29=0 28..27=3 vmimm vs2 14..12=7 6..0=0x27 -@vsuxb.s 26..25=2 vd rs1 29=1 28..27=3 vmimm vs2 14..12=0 6..0=0x27 -@vsuxh.s 26..25=2 vd rs1 29=1 28..27=3 vmimm vs2 14..12=5 6..0=0x27 -@vsuxw.s 26..25=2 vd rs1 29=1 28..27=3 vmimm vs2 14..12=6 6..0=0x27 -@vsuxe.s 26..25=2 vd rs1 29=1 28..27=3 vmimm vs2 14..12=7 6..0=0x27 +vlb.v vm vd rs1 29=1 28..27=0 vlimm vimm 14..12=0 6..0=0x07 +vlh.v vm vd rs1 29=1 28..27=0 vlimm vimm 14..12=5 6..0=0x07 +vlw.v vm vd rs1 29=1 28..27=0 vlimm vimm 14..12=6 6..0=0x07 +vle.v vm vd rs1 29=1 28..27=0 vlimm vimm 14..12=7 6..0=0x07 +vlbu.v vm vd rs1 29=0 28..27=0 vlimm vimm 14..12=0 6..0=0x07 +vlhu.v vm vd rs1 29=0 28..27=0 vlimm vimm 14..12=5 6..0=0x07 +vlwu.v vm vd rs1 29=0 28..27=0 vlimm vimm 14..12=6 6..0=0x07 +vleu.v vm vd rs1 29=0 28..27=0 vlimm vimm 14..12=7 6..0=0x07 + +vlsb.v vm vd rs1 29=1 28..27=2 vlimm rs2 14..12=0 6..0=0x07 +vlsh.v vm vd rs1 29=1 28..27=2 vlimm rs2 14..12=5 6..0=0x07 +vlsw.v vm vd rs1 29=1 28..27=2 vlimm rs2 14..12=6 6..0=0x07 +vlse.v vm vd rs1 29=1 28..27=2 vlimm rs2 14..12=7 6..0=0x07 +vlsbu.v vm vd rs1 29=0 28..27=2 vlimm rs2 14..12=0 6..0=0x07 +vlshu.v vm vd rs1 29=0 28..27=2 vlimm rs2 14..12=5 6..0=0x07 +vlswu.v vm vd rs1 29=0 28..27=2 vlimm rs2 14..12=6 6..0=0x07 +vlseu.v vm vd rs1 29=0 28..27=2 vlimm rs2 14..12=7 6..0=0x07 + +vlxb.v vm vd rs1 29=1 28..27=3 vlimm vs2 14..12=0 6..0=0x07 +vlxh.v vm vd rs1 29=1 28..27=3 vlimm vs2 14..12=5 6..0=0x07 +vlxw.v vm vd rs1 29=1 28..27=3 vlimm vs2 14..12=6 6..0=0x07 +vlxe.v vm vd rs1 29=1 28..27=3 vlimm vs2 14..12=7 6..0=0x07 +vlxbu.v vm vd rs1 29=0 28..27=3 vlimm vs2 14..12=0 6..0=0x07 +vlxhu.v vm vd rs1 29=0 28..27=3 vlimm vs2 14..12=5 6..0=0x07 +vlxwu.v vm vd rs1 29=0 28..27=3 vlimm vs2 14..12=6 6..0=0x07 +vlxeu.v vm vd rs1 29=0 28..27=3 vlimm vs2 14..12=7 6..0=0x07 + +@vlb.s 26..25=2 vd rs1 29=1 28..27=0 vlimm vimm 14..12=0 6..0=0x07 +@vlh.s 26..25=2 vd rs1 29=1 28..27=0 vlimm vimm 14..12=5 6..0=0x07 +@vlw.s 26..25=2 vd rs1 29=1 28..27=0 vlimm vimm 14..12=6 6..0=0x07 +@vle.s 26..25=2 vd rs1 29=1 28..27=0 vlimm vimm 14..12=7 6..0=0x07 +@vlbu.s 26..25=2 vd rs1 29=0 28..27=0 vlimm vimm 14..12=0 6..0=0x07 +@vlhu.s 26..25=2 vd rs1 29=0 28..27=0 vlimm vimm 14..12=5 6..0=0x07 +@vlwu.s 26..25=2 vd rs1 29=0 28..27=0 vlimm vimm 14..12=6 6..0=0x07 +@vleu.s 26..25=2 vd rs1 29=0 28..27=0 vlimm vimm 14..12=7 6..0=0x07 + +@vlsb.s 26..25=2 vd rs1 29=1 28..27=2 vlimm rs2 14..12=0 6..0=0x07 +@vlsh.s 26..25=2 vd rs1 29=1 28..27=2 vlimm rs2 14..12=5 6..0=0x07 +@vlsw.s 26..25=2 vd rs1 29=1 28..27=2 vlimm rs2 14..12=6 6..0=0x07 +@vlse.s 26..25=2 vd rs1 29=1 28..27=2 vlimm rs2 14..12=7 6..0=0x07 +@vlsbu.s 26..25=2 vd rs1 29=0 28..27=2 vlimm rs2 14..12=0 6..0=0x07 +@vlshu.s 26..25=2 vd rs1 29=0 28..27=2 vlimm rs2 14..12=5 6..0=0x07 +@vlswu.s 26..25=2 vd rs1 29=0 28..27=2 vlimm rs2 14..12=6 6..0=0x07 +@vlseu.s 26..25=2 vd rs1 29=0 28..27=2 vlimm rs2 14..12=7 6..0=0x07 + +@vlxb.s 26..25=2 vd rs1 29=1 28..27=3 vlimm vs2 14..12=0 6..0=0x07 +@vlxh.s 26..25=2 vd rs1 29=1 28..27=3 vlimm vs2 14..12=5 6..0=0x07 +@vlxw.s 26..25=2 vd rs1 29=1 28..27=3 vlimm vs2 14..12=6 6..0=0x07 +@vlxe.s 26..25=2 vd rs1 29=1 28..27=3 vlimm vs2 14..12=7 6..0=0x07 +@vlxbu.s 26..25=2 vd rs1 29=0 28..27=3 vlimm vs2 14..12=0 6..0=0x07 +@vlxhu.s 26..25=2 vd rs1 29=0 28..27=3 vlimm vs2 14..12=5 6..0=0x07 +@vlxwu.s 26..25=2 vd rs1 29=0 28..27=3 vlimm vs2 14..12=6 6..0=0x07 +@vlxeu.s 26..25=2 vd rs1 29=0 28..27=3 vlimm vs2 14..12=7 6..0=0x07 + +vsb.v vm vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=0 6..0=0x27 +vsh.v vm vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=5 6..0=0x27 +vsw.v vm vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=6 6..0=0x27 +vse.v vm vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=7 6..0=0x27 + +vssb.v vm vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=0 6..0=0x27 +vssh.v vm vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=5 6..0=0x27 +vssw.v vm vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=6 6..0=0x27 +vsse.v vm vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=7 6..0=0x27 + +vsxb.v vm vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=0 6..0=0x27 +vsxh.v vm vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=5 6..0=0x27 +vsxw.v vm vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=6 6..0=0x27 +vsxe.v vm vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=7 6..0=0x27 +vsuxb.v vm vs3 rs1 9=1 8..7=3 vsimm vs2 14..12=0 6..0=0x27 +vsuxh.v vm vs3 rs1 9=1 8..7=3 vsimm vs2 14..12=5 6..0=0x27 +vsuxw.v vm vs3 rs1 9=1 8..7=3 vsimm vs2 14..12=6 6..0=0x27 +vsuxe.v vm vs3 rs1 9=1 8..7=3 vsimm vs2 14..12=7 6..0=0x27 + +@vsb.s 26..25=2 vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=0 6..0=0x27 +@vsh.s 26..25=2 vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=5 6..0=0x27 +@vsw.s 26..25=2 vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=6 6..0=0x27 +@vse.s 26..25=2 vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=7 6..0=0x27 + +@vssb.s 26..25=2 vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=0 6..0=0x27 +@vssh.s 26..25=2 vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=5 6..0=0x27 +@vssw.s 26..25=2 vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=6 6..0=0x27 +@vsse.s 26..25=2 vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=7 6..0=0x27 + +@vsxb.s 26..25=2 vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=0 6..0=0x27 +@vsxh.s 26..25=2 vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=5 6..0=0x27 +@vsxw.s 26..25=2 vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=6 6..0=0x27 +@vsxe.s 26..25=2 vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=7 6..0=0x27 +@vsuxb.s 26..25=2 vs3 rs1 9=1 8..7=3 vsimm vs2 14..12=0 6..0=0x27 +@vsuxh.s 26..25=2 vs3 rs1 9=1 8..7=3 vsimm vs2 14..12=5 6..0=0x27 +@vsuxw.s 26..25=2 vs3 rs1 9=1 8..7=3 vsimm vs2 14..12=6 6..0=0x27 +@vsuxe.s 26..25=2 vs3 rs1 9=1 8..7=3 vsimm vs2 14..12=7 6..0=0x27 # Vector FMA vmadd.vvv vm vd vs1 vs2 vs3 14..12=0x5 6..2=0x10 1..0=3 diff --git a/parse-opcodes b/parse-opcodes index e586248..14919fa 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -37,8 +37,8 @@ arglut['vs3'] = (31,27) arglut['vop'] = (14,12) arglut['vm'] = (26,25) arglut['vimm'] = (24,20) -arglut['vmimm'] = (31,30) -arglut['vsimm'] = (11,11) +arglut['vlimm'] = (31,30) +arglut['vsimm'] = (11,10) arglut['vcimmhi'] = (26,20) arglut['vcimmlo'] = (14,12) @@ -621,7 +621,7 @@ def print_fence_type(name,match,arguments): def print_vi_type(name,match,arguments): #print """2+|%s|%s 2+|%s|%s|%s|%s 2+|%s|%s|%s""" % \ - print """2+|%s|%s|%s|%s|%s|%s|%s|%s""" % \ + print """2+|%s|%s|%s|%s|%s 2+|%s|%s|%s""" % \ ( \ binary(yank(match,27,5),5), \ str_arg('vm','',match,arguments), \ @@ -633,8 +633,8 @@ def print_vi_type(name,match,arguments): str_inst(name,arguments) \ ) -def print_vm_type(name,match,arguments): - print """|%s|%s|%s|%s|%s|%s|%s|%s|%s""" % \ +def print_vl_type(name,match,arguments): + print """|%s|%s|%s|%s|%s|%s 2+|%s|%s|%s""" % \ ( \ 'vimm' in arguments and 'imm[6:5]' or 'imm[1:0]', \ binary(yank(match,27,3),3), \ @@ -642,13 +642,27 @@ def print_vm_type(name,match,arguments): 'vimm'in arguments and 'imm[4:0]' or str_arg('rs2' in arguments and 'rs2' or 'vs2','',match,arguments), \ str_arg('rs1' in arguments and 'rs1' or 'vs1','',match,arguments), \ binary(yank(match,12,3),3), \ - 'vsimm' in arguments and 'imm[2:0]' or str_arg('vd','',match,arguments), \ + str_arg('vd','',match,arguments), \ + binary(yank(match,opcode_base,opcode_size),opcode_size), \ + str_inst(name,arguments) \ + ) + +def print_vs_type(name,match,arguments): + print """2+|%s|%s|%s|%s|%s|%s|%s|%s|%s""" % \ + ( \ + str_arg('rs3' in arguments and 'rs3' or 'vs3','',match,arguments), \ + str_arg('vm','m',match,arguments), \ + 'vimm'in arguments and 'imm[4:0]' or str_arg('rs2' in arguments and 'rs2' or 'vs2','',match,arguments), \ + str_arg('rs1' in arguments and 'rs1' or 'vs1','',match,arguments), \ + binary(yank(match,12,3),3), \ + 'vimm' in arguments and 'imm[6:5]' or 'imm[1:0]', \ + binary(yank(match,7,3),3), \ binary(yank(match,opcode_base,opcode_size),opcode_size), \ str_inst(name,arguments) \ ) def print_vr4_type(name,match,arguments): - print """2+|%s|%s|%s|%s|%s|%s|%s|%s""" % \ + print """2+|%s|%s|%s|%s|%s 2+|%s|%s|%s""" % \ ( \ str_arg('rs3' in arguments and 'rs3' or 'vs3','',match,arguments), \ str_arg('vm','',match,arguments), \ @@ -661,7 +675,7 @@ def print_vr4_type(name,match,arguments): ) def print_vr_type(name,match,arguments): - print """2+|%s|%s|%s|%s|%s|%s|%s|%s""" % \ + print """2+|%s|%s|%s|%s|%s 2+|%s|%s|%s""" % \ ( \ binary(yank(match,27,5),5), \ str_arg('vm','',match,arguments), \ @@ -782,9 +796,9 @@ def print_vec_subtitle(title): def print_vec_header(): print """ .Vector Table -[width="100%",cols="^3,^3,^3,^4,^4,^3,^4,^7,<10"] +[width="100%",cols="^3,^3,^3,^4,^4,^3,^3,^3,^7,<10"] |======================== -|31 30 |29 27 |26 25 |24 20 |19 15 |14 12 |11 7 |6 0 |Opcode +|31 30 |29 27 |26 25 |24 20 |19 15 |14 12 |11 10 |9 7 |6 0 |Opcode """ def print_vec_footer(): @@ -793,8 +807,10 @@ def print_vec_footer(): """ def print_vec_inst(n): - if 'vmimm' in arguments[n]: - print_vm_type(n, match[n], arguments[n]) + if 'vlimm' in arguments[n]: + print_vl_type(n, match[n], arguments[n]) + elif 'vsimm' in arguments[n]: + print_vs_type(n, match[n], arguments[n]) elif 'vimm' in arguments[n]: print_vi_type(n, match[n], arguments[n]) elif 'vs3' in arguments[n]: |