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| author | Andrew Waterman <andrew@sifive.com> | 2018-02-09 17:08:39 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-02-09 17:09:49 -0800 |
| commit | c7159b644a01c56851150b216c6fe2e2a730595e (patch) | |
| tree | 33e15eff0f6fdee36a45823465c38c31186963de | |
| parent | 19d6c637d1aeffd59dc08499d515061659cba1ad (diff) | |
| download | riscv-opcodes-c7159b644a01c56851150b216c6fe2e2a730595e.zip riscv-opcodes-c7159b644a01c56851150b216c6fe2e2a730595e.tar.gz riscv-opcodes-c7159b644a01c56851150b216c6fe2e2a730595e.tar.bz2 | |
Updates from most recent meeting
| -rw-r--r-- | opcodes-v | 10 | ||||
| -rwxr-xr-x | parse-opcodes | 9 |
2 files changed, 12 insertions, 7 deletions
@@ -25,7 +25,6 @@ vamomax m vd vs3 vs2 19..15=0x14 26..25=3 14=1 6..0=0x27 # First, all the immediates. vaddi m vd vs1 vimm 31..28=0 14=1 6..0=0x67 vsli m vd vs1 vimm 31..28=1 14=1 6..0=0x67 -vcvti m vd vs1 vimm 31..28=2 14=1 6..0=0x67 vclipi m vd vs1 vimm 31..28=3 14=1 6..0=0x67 vxori m vd vs1 vimm 31..28=4 14=1 6..0=0x67 vsri m vd vs1 vimm 31..28=5 14=1 6..0=0x67 @@ -54,13 +53,16 @@ vsge m vd vs1 vs2 27..25=7 31..28=9 14=1 6..0=0x67 # group 31..28=10 includes instructions that write xd # (and may also read xs1 and/or xs2). -vextract m rd vs1 rs2 27..25=1 31..28=10 14=1 6..0=0x67 +vextract m rd vs1 rs2 27..25=0 31..28=10 14=1 6..0=0x67 +vmfirst m rd vs1 27..25=7 31..28=10 14=1 6..0=0x67 24..20=0 +vmpop m rd vs1 27..25=7 31..28=10 14=1 6..0=0x67 24..20=1 # group 31..28=11 includes instructions that read xs1 and/or xs2, # but do not write xd. vclip m vd vs1 rs2 27..25=0 31..28=11 14=1 6..0=0x67 -vinsert m vd rs1 rs2 27..25=1 31..28=11 14=1 6..0=0x67 -vslide m vd rs1 rs2 27..25=2 31..28=11 14=1 6..0=0x67 +vcvt m vd vs1 rs2 27..25=1 31..28=11 14=1 6..0=0x67 +vslide m vd vs1 rs2 27..25=2 31..28=11 14=1 6..0=0x67 +vinsert m vd rs1 rs2 27..25=4 31..28=11 14=1 6..0=0x67 # group 31..28=12 vxor m vd vs1 vs2 27..25=0 31..28=12 14=1 6..0=0x67 diff --git a/parse-opcodes b/parse-opcodes index d13fe6d..8faf5a4 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -632,7 +632,7 @@ def print_vs_type(name,match,arguments): 'vlimm' in arguments and 'imm[4:0]' or str_arg('vs3','',match,arguments), \ binary(yank(match,25,2),2), \ str_arg('rs2' in arguments and 'rs2' or 'vs2','',match,arguments), \ - str_arg('rs1','',match,arguments), \ + str_arg('rs1' in arguments and 'rs1' or 'vs1','',match,arguments), \ binary(yank(match,14,1),1), \ str_arg('m','',match,arguments), \ 'vsimm' in arguments and 'imm[4:0]' or str_arg('vd','',match,arguments), \ @@ -918,14 +918,17 @@ def make_latex_table(): print_subtitle('RV32V Standard Extension', 9) print_insts('vadd', 'vsub', 'vsl', 'vsr', 'vand', 'vor', 'vxor') print_insts('vseq', 'vsne', 'vslt', 'vsge') - print_insts('vclip', 'vinsert', 'vextract', 'vmerge', 'vselect', 'vslide') + print_insts('vclip', 'vcvt', 'vmpop', 'vmfirst', 'vextract', 'vinsert', 'vmerge', 'vselect', 'vslide') print_insts('vdiv', 'vrem', 'vmul', 'vmulh') print_insts('vmin', 'vmax', 'vsgnj', 'vsgnjn', 'vsgnjx') print_insts('vsqrt', 'vclass') print_insts('vpopc') - print_insts('vcvti', 'vaddi', 'vsli', 'vsri', 'vandi', 'vori', 'vxori') + print_insts('vaddi', 'vsli', 'vsri', 'vandi', 'vori', 'vxori') print_insts('vclipi') print_insts('vmadd', 'vmsub', 'vnmadd', 'vnmsub') + print_footer() + print_vector_header() + print_subtitle('RV32V Standard Extension (cont.)', 9) print_insts('vld', 'vlds', 'vldx') print_insts('vst', 'vsts', 'vstx') print_insts('vamoswap', 'vamoadd', 'vamoand', 'vamoor', 'vamoxor', 'vamomin', 'vamomax') |