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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-02-05 18:15:50 -0800 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-02-05 18:15:50 -0800 |
commit | baed88131913ae48e3c84f7fdaa5549e5a698a07 (patch) | |
tree | 24a225897648d7dcf792178f2a2e6674a9fc45c3 | |
parent | cd97d2f441715dd31bb3fd079ab86dd957b5b4b0 (diff) | |
download | riscv-opcodes-baed88131913ae48e3c84f7fdaa5549e5a698a07.zip riscv-opcodes-baed88131913ae48e3c84f7fdaa5549e5a698a07.tar.gz riscv-opcodes-baed88131913ae48e3c84f7fdaa5549e5a698a07.tar.bz2 |
WIP on priv spec v1.9
-rw-r--r-- | encoding.h | 70 | ||||
-rw-r--r-- | opcodes | 9 | ||||
-rwxr-xr-x | parse-opcodes | 9 |
3 files changed, 44 insertions, 44 deletions
@@ -3,37 +3,41 @@ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H -#define MSTATUS_IE 0x00000001 -#define MSTATUS_PRV 0x00000006 -#define MSTATUS_IE1 0x00000008 -#define MSTATUS_PRV1 0x00000030 -#define MSTATUS_IE2 0x00000040 -#define MSTATUS_PRV2 0x00000180 -#define MSTATUS_IE3 0x00000200 -#define MSTATUS_PRV3 0x00000C00 -#define MSTATUS_FS 0x00003000 -#define MSTATUS_XS 0x0000C000 -#define MSTATUS_MPRV 0x00010000 -#define MSTATUS_VM 0x003E0000 +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_VM 0x007C0000 #define MSTATUS32_SD 0x80000000 #define MSTATUS64_SD 0x8000000000000000 -#define SSTATUS_IE 0x00000001 -#define SSTATUS_PIE 0x00000008 -#define SSTATUS_PS 0x00000010 -#define SSTATUS_FS 0x00003000 -#define SSTATUS_XS 0x0000C000 -#define SSTATUS_MPRV 0x00010000 -#define SSTATUS_TIE 0x01000000 +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_VM 0x007C0000 #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000 -#define MIP_SSIP 0x00000002 -#define MIP_HSIP 0x00000004 -#define MIP_MSIP 0x00000008 -#define MIP_STIP 0x00000020 -#define MIP_HTIP 0x00000040 -#define MIP_MTIP 0x00000080 +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP @@ -50,14 +54,14 @@ #define VM_SV39 9 #define VM_SV48 10 -#define UA_RV32 0 -#define UA_RV64 4 -#define UA_RV128 8 - -#define IRQ_SOFT 0 -#define IRQ_TIMER 1 -#define IRQ_HOST 2 -#define IRQ_COP 3 +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_COP 8 +#define IRQ_HOST 9 #define IMPL_ROCKET 1 @@ -115,12 +115,9 @@ sc.d rd rs1 rs2 aqrl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3 # SYSTEM scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 -sret 11..7=0 19..15=0 31..20=0x100 14..12=0 6..2=0x1C 1..0=3 -sfence.vm 11..7=0 rs1 31..20=0x101 14..12=0 6..2=0x1C 1..0=3 -wfi 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 -mrth 11..7=0 19..15=0 31..20=0x306 14..12=0 6..2=0x1C 1..0=3 -mrts 11..7=0 19..15=0 31..20=0x305 14..12=0 6..2=0x1C 1..0=3 -hrts 11..7=0 19..15=0 31..20=0x205 14..12=0 6..2=0x1C 1..0=3 +sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 +sfence.vm 11..7=0 rs1 31..20=0x104 14..12=0 6..2=0x1C 1..0=3 +wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3 csrrw rd rs1 imm12 14..12=1 6..2=0x1C 1..0=3 csrrs rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3 csrrc rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3 diff --git a/parse-opcodes b/parse-opcodes index ffc1f07..b34e282 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -84,6 +84,8 @@ csrs = [ (0x104, 'sie'), (0x140, 'sscratch'), (0x141, 'sepc'), + (0x142, 'scause'), + (0x143, 'sbadaddr'), (0x144, 'sip'), (0x180, 'sptbr'), (0x181, 'sasid'), @@ -95,8 +97,6 @@ csrs = [ # Standard Supervisor RO (0xD01, 'stime'), - (0xD42, 'scause'), - (0xD43, 'sbadaddr'), # Standard Hypervisor R/W Shadows of Supervisor RO (0xA01, 'stimew'), @@ -104,7 +104,8 @@ csrs = [ # Standard Machine R/W (0x300, 'mstatus'), (0x301, 'mtvec'), - (0x302, 'mtdeleg'), + (0x302, 'medeleg'), + (0x303, 'mideleg'), (0x304, 'mie'), (0x321, 'mtimecmp'), (0x340, 'mscratch'), @@ -648,8 +649,6 @@ def make_supervisor_latex_table(): print_insts('csrrwi', 'csrrsi', 'csrrci') print_subtitle('Instructions to Change Privilege Level') print_insts('ecall', 'ebreak', 'eret') - print_subtitle('Trap-Redirection Instructions') - print_insts('mrts', 'mrth', 'hrts') print_subtitle('Interrupt-Management Instructions') print_insts('wfi') print_subtitle('Memory-Management Instructions') |