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authorColin Schmidt <colins@berkeley.edu>2018-12-21 09:27:49 +0530
committerColin Schmidt <colins@berkeley.edu>2018-12-21 09:27:49 +0530
commit5989d0d743185b54e60e98a23390c01624826fa4 (patch)
tree67fe77526c4557aaab78d15b23c4f331fb8a92fa
parent4cba3c4a91ee386062cc67933608fbb77c509af4 (diff)
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Add vsetvli encoding
-rw-r--r--opcodes-v6
-rwxr-xr-xparse-opcodes4
2 files changed, 8 insertions, 2 deletions
diff --git a/opcodes-v b/opcodes-v
index 40fcb50..5b75828 100644
--- a/opcodes-v
+++ b/opcodes-v
@@ -239,6 +239,7 @@ vmsbf.v vm vd vs1 24..20=0 14=0 12=1 31..27=0x1B 13=1 6..0=0x57
vmsif.v vm vd vs1 24..20=1 14=0 12=1 31..27=0x1B 13=1 6..0=0x57
vmsof.v vm vd vs1 24..20=2 14=0 12=1 31..27=0x1B 13=1 6..0=0x57
+#Only destination ops
viota.v vm vd 19..15=0 24..20=0x1F 14..12=0 31..27=0x1B 6..0=0x57
vfsgnj.vv vm vd vs1 vs2 14=0 12=0 31..27=0x1C 13=0 6..0=0x57
@@ -262,6 +263,9 @@ vfmax.vi vm vd vs1 vimm 14=1 12=1 31..27=0x1E 13=1 6..0=0x57
vmerge.vv vm vd vs1 vs2 14=0 12=0 31..27=0x1F 13=0 6..0=0x57
vmerge.vs vm vd vs1 vs2 14=1 12=0 31..27=0x1F 13=0 6..0=0x57
vmerge.vi vm vd vs1 vimm 14=1 12=1 31..27=0x1F 13=0 6..0=0x57
+vselect.vv vm vd vs1 vs2 14=0 12=0 31..27=0x1F 13=1 6..0=0x57
+vselect.vs vm vd vs1 vs2 14=1 12=0 31..27=0x1F 13=1 6..0=0x57
+vselect.vi vm vd vs1 vimm 14=1 12=1 31..27=0x1F 13=1 6..0=0x57
vmv.x.v rd vs1 rs2 26..25=0 14..12=0 31..27=0x0D 6..0=0x57
vmv.v.x vd rs1 rs2 26..25=1 14..12=0 31..27=0x0D 6..0=0x57
@@ -287,6 +291,6 @@ vredand.v vm vd vs1 vs2 14..12=0 31..27=0x0F 6..0=0x57
vredor.v vm vd vs1 vs2 14..12=1 31..27=0x0F 6..0=0x57
vredxor.v vm vd vs1 vs2 14..12=2 31..27=0x0F 6..0=0x57
+vsetvli rd rs1 vcimmhi vcimmlo 31..27=0x02 6..0=0x57
# TODO(Colin): These need an encoding
###vselect m vd vs1 vs2 27..25=2 31..28=12 14=1 6..0=0x57
-###vsetvli vd vs1 24..20=0 27..25=0 31..28=15 14=1 13..12=0 6..0=0x57
diff --git a/parse-opcodes b/parse-opcodes
index e6aad75..e586248 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -39,6 +39,8 @@ arglut['vm'] = (26,25)
arglut['vimm'] = (24,20)
arglut['vmimm'] = (31,30)
arglut['vsimm'] = (11,11)
+arglut['vcimmhi'] = (26,20)
+arglut['vcimmlo'] = (14,12)
causes = [
(0x00, 'misaligned fetch'),
@@ -979,7 +981,7 @@ def make_vector_adoc_table():
print_vec_insts('vssb.s', 'vssh.s', 'vssw.s', 'vsse.s')
print_vec_insts('vsxb.s', 'vsxh.s', 'vsxw.s', 'vsxe.s', 'vsuxb.s', 'vsuxh.s', 'vsuxw.s', 'vsuxe.s')
- #print_vec_insts('vsetvl', 'vconfig')
+ #print_vec_insts('vsetvli')
print_vec_footer()
def print_chisel_insn(name):