diff options
| author | Colin Schmidt <colins@eecs.berkeley.edu> | 2018-10-30 20:46:12 -0700 |
|---|---|---|
| committer | Colin Schmidt <colins@eecs.berkeley.edu> | 2018-10-30 20:46:12 -0700 |
| commit | 4cfdce39025d0b1946b7d04ed9229330aa1d8649 (patch) | |
| tree | 3de3740fa0d9f336792f289aa05bf95d2f204cfb | |
| parent | f4d33eb18c572893ab0519999365ac4b196b2c27 (diff) | |
| download | riscv-opcodes-4cfdce39025d0b1946b7d04ed9229330aa1d8649.zip riscv-opcodes-4cfdce39025d0b1946b7d04ed9229330aa1d8649.tar.gz riscv-opcodes-4cfdce39025d0b1946b7d04ed9229330aa1d8649.tar.bz2 | |
Add logical shifts to follow spec
| -rw-r--r-- | opcodes-v | 8 | ||||
| -rwxr-xr-x | parse-opcodes | 2 |
2 files changed, 5 insertions, 5 deletions
@@ -140,9 +140,10 @@ vmulhsu m vd vs1 vs2 27..25=7 31..28=8 14=1 6..0=0x57 # group 31..28=9 vsl m vd vs1 vs2 27..25=0 31..28=9 14=1 6..0=0x57 -vsr m vd vs1 vs2 27..25=1 31..28=9 14=1 6..0=0x57 -vor m vd vs1 vs2 27..25=2 31..28=9 14=1 6..0=0x57 -vand m vd vs1 vs2 27..25=3 31..28=9 14=1 6..0=0x57 +vsrl m vd vs1 vs2 27..25=1 31..28=9 14=1 6..0=0x57 +vsra m vd vs1 vs2 27..25=2 31..28=9 14=1 6..0=0x57 +vor m vd vs1 vs2 27..25=3 31..28=9 14=1 6..0=0x57 +vand m vd vs1 vs2 27..25=4 31..28=9 14=1 6..0=0x57 # group 31..28=10 includes instructions that write xd # (and may also read xs1 and/or xs2). @@ -165,7 +166,6 @@ vselect m vd vs1 vs2 27..25=2 31..28=12 14=1 6..0=0x57 # group 31..28=12, 27..25=7 is for single-argument instructions. vclass m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=0 vpopc m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=1 -vsqrt m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=2 vneg m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=3 vredsum m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=4 vredmax m vd vs1 27..25=7 31..28=12 14=1 6..0=0x57 24..20=5 diff --git a/parse-opcodes b/parse-opcodes index c09ee59..7618dc4 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -953,7 +953,7 @@ def make_latex_table(): def make_vector_adoc_table(): #print_vec_subtitile('RV32V Standard Extension') print_vec_header() - print_vec_insts('vadd', 'vsub', 'vsl', 'vsr', 'vand', 'vor', 'vxor', 'vneg') + print_vec_insts('vadd', 'vsub', 'vsl', 'vsrl', 'vsra', 'vand', 'vor', 'vxor', 'vneg') print_vec_insts('vseq', 'vsne', 'vslt', 'vsge', 'vsltu', 'vsgeu') print_vec_insts('vclip', 'vcvt', 'vmpop', 'vmfirst', 'vextract', 'vinsert', 'vmerge', 'vselect', 'vslide', 'vrgather') print_vec_insts('vdiv', 'vrem', 'vmul', 'vmulh', 'vmulhu', 'vmulhsu') |