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| author | Colin Schmidt <colins@berkeley.edu> | 2018-12-22 09:31:25 +0530 |
|---|---|---|
| committer | Colin Schmidt <colins@berkeley.edu> | 2018-12-22 09:31:25 +0530 |
| commit | 077157ad30b7c2cf484e307f9cc2e2b3a26e9ec9 (patch) | |
| tree | 24a00b1e946e5d5c1f76928fa83510a61e0a723c | |
| parent | daf66b12224030a7eb9210bba53151d9df5f9ee9 (diff) | |
| download | riscv-opcodes-077157ad30b7c2cf484e307f9cc2e2b3a26e9ec9.zip riscv-opcodes-077157ad30b7c2cf484e307f9cc2e2b3a26e9ec9.tar.gz riscv-opcodes-077157ad30b7c2cf484e307f9cc2e2b3a26e9ec9.tar.bz2 | |
Add remaining unordered stores
| -rw-r--r-- | opcodes-v | 18 | ||||
| -rwxr-xr-x | parse-opcodes | 8 |
2 files changed, 20 insertions, 6 deletions
@@ -57,11 +57,19 @@ vsb.v vm vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=0 6..0=0x27 vsh.v vm vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=5 6..0=0x27 vsw.v vm vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=6 6..0=0x27 vse.v vm vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=7 6..0=0x27 +vsub.v vm vs3 rs1 9=1 8..7=0 vsimm vimm 14..12=0 6..0=0x27 +vsuh.v vm vs3 rs1 9=1 8..7=0 vsimm vimm 14..12=5 6..0=0x27 +vsuw.v vm vs3 rs1 9=1 8..7=0 vsimm vimm 14..12=6 6..0=0x27 +vsue.v vm vs3 rs1 9=1 8..7=0 vsimm vimm 14..12=7 6..0=0x27 vssb.v vm vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=0 6..0=0x27 vssh.v vm vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=5 6..0=0x27 vssw.v vm vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=6 6..0=0x27 vsse.v vm vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=7 6..0=0x27 +vsusb.v vm vs3 rs1 9=1 8..7=2 vsimm rs2 14..12=0 6..0=0x27 +vsush.v vm vs3 rs1 9=1 8..7=2 vsimm rs2 14..12=5 6..0=0x27 +vsusw.v vm vs3 rs1 9=1 8..7=2 vsimm rs2 14..12=6 6..0=0x27 +vsuse.v vm vs3 rs1 9=1 8..7=2 vsimm rs2 14..12=7 6..0=0x27 vsxb.v vm vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=0 6..0=0x27 vsxh.v vm vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=5 6..0=0x27 @@ -76,11 +84,19 @@ vsuxe.v vm vs3 rs1 9=1 8..7=3 vsimm vs2 14..12=7 6..0=0x27 @vsh.s 26..25=2 vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=5 6..0=0x27 @vsw.s 26..25=2 vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=6 6..0=0x27 @vse.s 26..25=2 vs3 rs1 9=0 8..7=0 vsimm vimm 14..12=7 6..0=0x27 +@vsub.s 26..25=2 vs3 rs1 9=1 8..7=0 vsimm vimm 14..12=0 6..0=0x27 +@vsuh.s 26..25=2 vs3 rs1 9=1 8..7=0 vsimm vimm 14..12=5 6..0=0x27 +@vsuw.s 26..25=2 vs3 rs1 9=1 8..7=0 vsimm vimm 14..12=6 6..0=0x27 +@vsue.s 26..25=2 vs3 rs1 9=1 8..7=0 vsimm vimm 14..12=7 6..0=0x27 @vssb.s 26..25=2 vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=0 6..0=0x27 @vssh.s 26..25=2 vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=5 6..0=0x27 @vssw.s 26..25=2 vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=6 6..0=0x27 @vsse.s 26..25=2 vs3 rs1 9=0 8..7=2 vsimm rs2 14..12=7 6..0=0x27 +@vsusb.s 26..25=2 vs3 rs1 9=1 8..7=2 vsimm rs2 14..12=0 6..0=0x27 +@vsush.s 26..25=2 vs3 rs1 9=1 8..7=2 vsimm rs2 14..12=5 6..0=0x27 +@vsusw.s 26..25=2 vs3 rs1 9=1 8..7=2 vsimm rs2 14..12=6 6..0=0x27 +@vsuse.s 26..25=2 vs3 rs1 9=1 8..7=2 vsimm rs2 14..12=7 6..0=0x27 @vsxb.s 26..25=2 vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=0 6..0=0x27 @vsxh.s 26..25=2 vs3 rs1 9=0 8..7=3 vsimm vs2 14..12=5 6..0=0x27 @@ -292,5 +308,3 @@ vredor.v vm vd vs1 vs2 14..12=1 31..27=0x0F 6..0=0x57 vredxor.v vm vd vs1 vs2 14..12=2 31..27=0x0F 6..0=0x57 vsetvli rd rs1 vcimmhi vcimmlo 31..27=0x02 6..0=0x57 -# TODO(Colin): These need an encoding -###vselect m vd vs1 vs2 27..25=2 31..28=12 14=1 6..0=0x57 diff --git a/parse-opcodes b/parse-opcodes index 14919fa..46bc01b 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -989,12 +989,12 @@ def make_vector_adoc_table(): print_vec_insts('vlsb.s', 'vlsh.s', 'vlsw.s', 'vlse.s', 'vlsbu.s', 'vlshu.s', 'vlswu.s', 'vlseu.s') print_vec_insts('vlxb.s', 'vlxh.s', 'vlxw.s', 'vlxe.s', 'vlxbu.s', 'vlxhu.s', 'vlxwu.s', 'vlxeu.s') - print_vec_insts('vsb.v', 'vsh.v', 'vsw.v', 'vse.v') - print_vec_insts('vssb.v', 'vssh.v', 'vssw.v', 'vsse.v') + print_vec_insts('vsb.v', 'vsh.v', 'vsw.v', 'vse.v', 'vsub.v', 'vsuh.v', 'vsuw.v', 'vsue.v') + print_vec_insts('vssb.v', 'vssh.v', 'vssw.v', 'vsse.v', 'vsusb.v', 'vsush.v', 'vsusw.v', 'vsuse.v') print_vec_insts('vsxb.v', 'vsxh.v', 'vsxw.v', 'vsxe.v', 'vsuxb.v', 'vsuxh.v', 'vsuxw.v', 'vsuxe.v') - print_vec_insts('vsb.s', 'vsh.s', 'vsw.s', 'vse.s') - print_vec_insts('vssb.s', 'vssh.s', 'vssw.s', 'vsse.s') + print_vec_insts('vsb.s', 'vsh.s', 'vsw.s', 'vse.s', 'vsub.s', 'vsuh.s', 'vsuw.s', 'vsue.s') + print_vec_insts('vssb.s', 'vssh.s', 'vssw.s', 'vsse.s', 'vsusb.s', 'vsush.s', 'vsusw.s', 'vsuse.s') print_vec_insts('vsxb.s', 'vsxh.s', 'vsxw.s', 'vsxe.s', 'vsuxb.s', 'vsuxh.s', 'vsuxw.s', 'vsuxe.s') #print_vec_insts('vsetvli') |