blob: 4b35905ce4e40a47e83b1634edd949a55d6422f5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
|
[submodule "riscv-isa-sim"]
path = riscv-isa-sim
url = https://github.com/ucb-bar/riscv-isa-sim.git
[submodule "riscv-fesvr"]
path = riscv-fesvr
url = https://github.com/ucb-bar/riscv-fesvr.git
[submodule "riscv-pk"]
path = riscv-pk
url = https://github.com/ucb-bar/riscv-pk.git
[submodule "riscv-gcc"]
path = riscv-gcc
url = https://github.com/ucb-bar/riscv-gcc.git
[submodule "riscv-opcodes"]
path = riscv-opcodes
url = https://github.com/ucb-bar/riscv-opcodes.git
[submodule "riscv-tests"]
path = riscv-tests
url = https://github.com/ucb-bar/riscv-tests.git
[submodule "riscv-llvm"]
path = riscv-llvm
url = https://github.com/ucb-bar/riscv-llvm.git
[submodule "riscv-qemu"]
path = riscv-qemu
url = https://github.com/ucb-bar/riscv-qemu.git
|