From ed2db7918d571b75c4075ef318b4e601004c6424 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 9 Mar 2017 12:44:28 -0800
Subject: WIP on priv-1.10

---
 riscv-fesvr         | 2 +-
 riscv-gnu-toolchain | 2 +-
 riscv-isa-sim       | 2 +-
 riscv-opcodes       | 2 +-
 riscv-pk            | 2 +-
 riscv-tests         | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/riscv-fesvr b/riscv-fesvr
index 0b85715..e05b488 160000
--- a/riscv-fesvr
+++ b/riscv-fesvr
@@ -1 +1 @@
-Subproject commit 0b85715f43196e858cc965559914efba7561f453
+Subproject commit e05b488086f25d79ac9cd7ab866b04f7d1fe8213
diff --git a/riscv-gnu-toolchain b/riscv-gnu-toolchain
index 914224e..010fac4 160000
--- a/riscv-gnu-toolchain
+++ b/riscv-gnu-toolchain
@@ -1 +1 @@
-Subproject commit 914224e0913c9ceab49ad9531a7fedc231f65c15
+Subproject commit 010fac4fcbb54e014cfc21632a39b59ab66b412b
diff --git a/riscv-isa-sim b/riscv-isa-sim
index f38dcde..3c8dafe 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit f38dcde0d80d2f4818b8f20067b8de5267c8ade6
+Subproject commit 3c8dafeef056dec71e731fe097750391fe1dfc25
diff --git a/riscv-opcodes b/riscv-opcodes
index 7650b39..2536e52 160000
--- a/riscv-opcodes
+++ b/riscv-opcodes
@@ -1 +1 @@
-Subproject commit 7650b391d47dd0b73d541d39c48041aa53517973
+Subproject commit 2536e5268c031d734e2334e4d9afde1b8517db1b
diff --git a/riscv-pk b/riscv-pk
index f6b2274..36a5855 160000
--- a/riscv-pk
+++ b/riscv-pk
@@ -1 +1 @@
-Subproject commit f6b2274af4a91763ecdb94600d7d54d5f7f262b5
+Subproject commit 36a5855d446efab2d122346c99e12b66183a2e9b
diff --git a/riscv-tests b/riscv-tests
index 6a1a38d..db0b30a 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 6a1a38d421fd3e24bdc179d58d33572636b903b2
+Subproject commit db0b30ac92e3f5b639d0a9eda73e20cddc4e85a9
-- 
cgit v1.1


From d68233394ed0c16032afc0e65cb622e3e18f0f7e Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 15 Mar 2017 14:24:00 -0700
Subject: Use correct --host setting for riscv-pk/configure

---
 build-spike-pk.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/build-spike-pk.sh b/build-spike-pk.sh
index 00af1d5..02f3202 100755
--- a/build-spike-pk.sh
+++ b/build-spike-pk.sh
@@ -15,6 +15,6 @@ echo "Starting RISC-V Toolchain build process"
 
 build_project riscv-fesvr --prefix=$RISCV
 build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV
-CC=riscv64-unknown-elf-gcc build_project riscv-pk --prefix=$RISCV/riscv64-unknown-elf --host=riscv
+CC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv64-unknown-elf
 
 echo -e "\\nRISC-V Toolchain installation completed!"
-- 
cgit v1.1


From 111ed8877e1d32b908bbf3b5f6eaba3f2a8bd14a Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Tue, 21 Mar 2017 16:52:05 -0700
Subject: README: add device-tree-compiler dependency

---
 README.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
index efdb294..6673918 100644
--- a/README.md
+++ b/README.md
@@ -22,7 +22,7 @@ This repo provides guides and references:
 
 Ubuntu packages needed:
 
-	$ sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev
+	$ sudo apt-get install autoconf automake autotools-dev curl device-tree-compiler libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev
 
 
 _Note:_ This requires a compiler with C++11 support (e.g. GCC >= 4.8).
@@ -30,7 +30,7 @@ To use a compiler different than the default, use:
 
 	$ CC=gcc-5 CXX=g++-5 ./build.sh
 
-_Note for OS X:_ We recommend using [Homebrew](http://brew.sh) to install the dependencies (`gawk gnu-sed gmp mpfr libmpc isl wget`) or even to install the tools [directly](https://github.com/riscv/homebrew-riscv). This repo will build with Apple's command-line developer tools (clang) in addition to gcc.
+_Note for OS X:_ We recommend using [Homebrew](http://brew.sh) to install the dependencies (`dtc gawk gnu-sed gmp mpfr libmpc isl wget`) or even to install the tools [directly](https://github.com/riscv/homebrew-riscv). This repo will build with Apple's command-line developer tools (clang) in addition to gcc.
 
 
 # <a name="newlibman"></a>The RISC-V GCC/Newlib Toolchain Installation Manual
@@ -191,7 +191,7 @@ flex, bison, autotools, libmpc, libmpfr, and libgmp. Ubuntu distribution
 installations will require this command to be run. If you have not installed
 these things yet, then run this:
 
-	O$ sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc
+	O$ sudo apt-get install autoconf automake autotools-dev curl device-tree-compiler libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc
 
 Before we start installation, we need to set the
 `$RISCV` environment variable. The variable is used throughout the
@@ -394,7 +394,7 @@ flex, bison, autotools, libmpc, libmpfr, and libgmp. Ubuntu distribution
 installations will require this command to be run. If you have not installed
 these things yet, then run this:
 
-	O$ sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf
+	O$ sudo apt-get install autoconf automake autotools-dev curl device-tree-compiler libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf
 
 Before we start installation, we need to set the
 `$RISCV` environment variable. The variable is used throughout the
-- 
cgit v1.1


From 9274ad6aaca5833b8d36788b8362e71a4b0c7a1a Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 23 Mar 2017 13:26:09 -0700
Subject: WIP on priv-1.10

---
 riscv-fesvr         | 2 +-
 riscv-gnu-toolchain | 2 +-
 riscv-isa-sim       | 2 +-
 riscv-opcodes       | 2 +-
 riscv-pk            | 2 +-
 riscv-tests         | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/riscv-fesvr b/riscv-fesvr
index e05b488..7ec5a01 160000
--- a/riscv-fesvr
+++ b/riscv-fesvr
@@ -1 +1 @@
-Subproject commit e05b488086f25d79ac9cd7ab866b04f7d1fe8213
+Subproject commit 7ec5a019cbd25eb94ff32892ee2ca8e20ab16694
diff --git a/riscv-gnu-toolchain b/riscv-gnu-toolchain
index 010fac4..afe9c81 160000
--- a/riscv-gnu-toolchain
+++ b/riscv-gnu-toolchain
@@ -1 +1 @@
-Subproject commit 010fac4fcbb54e014cfc21632a39b59ab66b412b
+Subproject commit afe9c81cdb4d84d6f954fb8231909bc10631be98
diff --git a/riscv-isa-sim b/riscv-isa-sim
index 3c8dafe..e83a032 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit 3c8dafeef056dec71e731fe097750391fe1dfc25
+Subproject commit e83a032060865550e33659a69a86870f9da880b1
diff --git a/riscv-opcodes b/riscv-opcodes
index 2536e52..771cd8a 160000
--- a/riscv-opcodes
+++ b/riscv-opcodes
@@ -1 +1 @@
-Subproject commit 2536e5268c031d734e2334e4d9afde1b8517db1b
+Subproject commit 771cd8afc10b438c1e7e8109287d40cb6bd3eddb
diff --git a/riscv-pk b/riscv-pk
index 36a5855..fc1af65 160000
--- a/riscv-pk
+++ b/riscv-pk
@@ -1 +1 @@
-Subproject commit 36a5855d446efab2d122346c99e12b66183a2e9b
+Subproject commit fc1af65c1585b2a9ad1dd2cf1b50d552ee65c742
diff --git a/riscv-tests b/riscv-tests
index db0b30a..fd03c71 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit db0b30ac92e3f5b639d0a9eda73e20cddc4e85a9
+Subproject commit fd03c714d638d826bcff8e3c80c58a01ba39510d
-- 
cgit v1.1


From e15160d13aca4c007bcab70375eb438d7a204562 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 23 Mar 2017 18:00:18 -0700
Subject: Disable debug tests for now

---
 .travis.yml         | 4 ++--
 riscv-gnu-toolchain | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index dd5c935..9ade992 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -45,5 +45,5 @@ install: travis_wait
 
 script:
   - ./build.sh
-  - cd riscv-tests/build
-  - make debug-check
+  #- cd riscv-tests/build
+  #- make debug-check
diff --git a/riscv-gnu-toolchain b/riscv-gnu-toolchain
index afe9c81..2490d7c 160000
--- a/riscv-gnu-toolchain
+++ b/riscv-gnu-toolchain
@@ -1 +1 @@
-Subproject commit afe9c81cdb4d84d6f954fb8231909bc10631be98
+Subproject commit 2490d7caf46cc4a84e267315534a2242e9a86b25
-- 
cgit v1.1


From 24ce6c0870755bd2af1bc39887ab84684c5ce586 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Fri, 24 Mar 2017 12:59:03 -0700
Subject: bump tests

---
 riscv-tests | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-tests b/riscv-tests
index fd03c71..8aebc7e 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit fd03c714d638d826bcff8e3c80c58a01ba39510d
+Subproject commit 8aebc7e29009096e0c5bd2a3ab7bc31271647020
-- 
cgit v1.1


From 4f430b184ed07890cd30ad144ded6d7cb07dcdf0 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Sun, 26 Mar 2017 11:29:20 -0700
Subject: Bump spike, tests, pk

---
 riscv-isa-sim | 2 +-
 riscv-pk      | 2 +-
 riscv-tests   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/riscv-isa-sim b/riscv-isa-sim
index e83a032..1fa2174 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit e83a032060865550e33659a69a86870f9da880b1
+Subproject commit 1fa2174178a5432443f114dfc059ba19c53b1fae
diff --git a/riscv-pk b/riscv-pk
index fc1af65..96e5ed7 160000
--- a/riscv-pk
+++ b/riscv-pk
@@ -1 +1 @@
-Subproject commit fc1af65c1585b2a9ad1dd2cf1b50d552ee65c742
+Subproject commit 96e5ed750e7447f2c0316368e5592fd331ee345c
diff --git a/riscv-tests b/riscv-tests
index 8aebc7e..f9e8b26 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 8aebc7e29009096e0c5bd2a3ab7bc31271647020
+Subproject commit f9e8b267a273eb704f6def6f0fa04140d0654d18
-- 
cgit v1.1


From 89d487023c1e59ff574872e2f51ee479cda380ab Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 27 Mar 2017 14:31:26 -0700
Subject: Separate page faults from physical memory access exceptions

---
 riscv-gnu-toolchain | 2 +-
 riscv-isa-sim       | 2 +-
 riscv-opcodes       | 2 +-
 riscv-pk            | 2 +-
 riscv-tests         | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/riscv-gnu-toolchain b/riscv-gnu-toolchain
index 2490d7c..8b16c61 160000
--- a/riscv-gnu-toolchain
+++ b/riscv-gnu-toolchain
@@ -1 +1 @@
-Subproject commit 2490d7caf46cc4a84e267315534a2242e9a86b25
+Subproject commit 8b16c6123d3dc9642ceeaa6ad371f494d5970873
diff --git a/riscv-isa-sim b/riscv-isa-sim
index 1fa2174..a80c695 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit 1fa2174178a5432443f114dfc059ba19c53b1fae
+Subproject commit a80c695b1961ac40086494920f82e85a085ff358
diff --git a/riscv-opcodes b/riscv-opcodes
index 771cd8a..d86c50a 160000
--- a/riscv-opcodes
+++ b/riscv-opcodes
@@ -1 +1 @@
-Subproject commit 771cd8afc10b438c1e7e8109287d40cb6bd3eddb
+Subproject commit d86c50a5a6f44ed4b0e5506dbbd782fed3f1fedd
diff --git a/riscv-pk b/riscv-pk
index 96e5ed7..3473915 160000
--- a/riscv-pk
+++ b/riscv-pk
@@ -1 +1 @@
-Subproject commit 96e5ed750e7447f2c0316368e5592fd331ee345c
+Subproject commit 3473915b3a3fd925a68fc3260c64824cab2846d2
diff --git a/riscv-tests b/riscv-tests
index f9e8b26..1b78e24 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit f9e8b267a273eb704f6def6f0fa04140d0654d18
+Subproject commit 1b78e242657f80250292f39e1f41bad2b1ab9d6c
-- 
cgit v1.1


From adf1cb4a75eebed12bf64cbcd38ceccc50721552 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Tue, 28 Mar 2017 21:12:32 -0700
Subject: debug: Bump FESVR version to initial Debug v13. Doesn't work yet.

---
 riscv-fesvr | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-fesvr b/riscv-fesvr
index 7ec5a01..bdc0e5d 160000
--- a/riscv-fesvr
+++ b/riscv-fesvr
@@ -1 +1 @@
-Subproject commit 7ec5a019cbd25eb94ff32892ee2ca8e20ab16694
+Subproject commit bdc0e5d3138be7ea16a5ba4f8be4b4f9999338e5
-- 
cgit v1.1


From 70a6a0851c5ac0f8749df83d1876f15df9419755 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 29 Mar 2017 14:45:26 -0700
Subject: debug: Bump FESVR to version that works with debug v013

---
 riscv-fesvr | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-fesvr b/riscv-fesvr
index bdc0e5d..f0a49de 160000
--- a/riscv-fesvr
+++ b/riscv-fesvr
@@ -1 +1 @@
-Subproject commit bdc0e5d3138be7ea16a5ba4f8be4b4f9999338e5
+Subproject commit f0a49ded4fa0063dd63441a26e180d415519d842
-- 
cgit v1.1


From eba11b0de2a8e7500b3a1c075c5ac49da718680e Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 29 Mar 2017 15:12:50 -0700
Subject: debug_v013: bump fesvr for minor off-by-1 fix

---
 riscv-fesvr | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-fesvr b/riscv-fesvr
index f0a49de..c2192dc 160000
--- a/riscv-fesvr
+++ b/riscv-fesvr
@@ -1 +1 @@
-Subproject commit f0a49ded4fa0063dd63441a26e180d415519d842
+Subproject commit c2192dc389391acb1bc02216c7ed227e21a1ccb5
-- 
cgit v1.1


From af8f5ee2fc951a4a0b030e4a8d82fc4b1a1571e2 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 29 Mar 2017 21:41:13 -0700
Subject: debug_v013: FESVR only read/write relevant DATA registers

---
 riscv-fesvr | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-fesvr b/riscv-fesvr
index c2192dc..1e447de 160000
--- a/riscv-fesvr
+++ b/riscv-fesvr
@@ -1 +1 @@
-Subproject commit c2192dc389391acb1bc02216c7ed227e21a1ccb5
+Subproject commit 1e447deb33a69758f0a46fa5a7f0f45c5730d892
-- 
cgit v1.1


From decf42b0f357220adb6722ddba362c6884321477 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 30 Mar 2017 00:30:56 -0700
Subject: New PMP encoding

---
 riscv-isa-sim | 2 +-
 riscv-opcodes | 2 +-
 riscv-pk      | 2 +-
 riscv-tests   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/riscv-isa-sim b/riscv-isa-sim
index a80c695..b04dfe3 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit a80c695b1961ac40086494920f82e85a085ff358
+Subproject commit b04dfe31de85923faf4c701ec2fcf7ff0afc6de7
diff --git a/riscv-opcodes b/riscv-opcodes
index d86c50a..e4c9357 160000
--- a/riscv-opcodes
+++ b/riscv-opcodes
@@ -1 +1 @@
-Subproject commit d86c50a5a6f44ed4b0e5506dbbd782fed3f1fedd
+Subproject commit e4c935733f653d97913fb0418abfa89f6f3d90d2
diff --git a/riscv-pk b/riscv-pk
index 3473915..078ea39 160000
--- a/riscv-pk
+++ b/riscv-pk
@@ -1 +1 @@
-Subproject commit 3473915b3a3fd925a68fc3260c64824cab2846d2
+Subproject commit 078ea399c6c1f2d6e8461559bf8cc1ba34ca89b6
diff --git a/riscv-tests b/riscv-tests
index 1b78e24..c066a09 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 1b78e242657f80250292f39e1f41bad2b1ab9d6c
+Subproject commit c066a09ce18eb9252892d105386b40fa80242120
-- 
cgit v1.1


From 6e32ffa7a4e03254f934623f083078f82a721be7 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 30 Mar 2017 11:45:48 -0700
Subject: debug_v013: bump fesvr to use autoexec feature for memory writes.

---
 riscv-fesvr | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-fesvr b/riscv-fesvr
index 1e447de..6ff5489 160000
--- a/riscv-fesvr
+++ b/riscv-fesvr
@@ -1 +1 @@
-Subproject commit 1e447deb33a69758f0a46fa5a7f0f45c5730d892
+Subproject commit 6ff5489612887b4bc57aad0e8821990f6d0513ac
-- 
cgit v1.1


From 91f9934900abac7ab587b342aec1ed03a602acc5 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 30 Mar 2017 15:55:42 -0700
Subject: debug_v013: bump fesvr now that it points to code for Debug v013

---
 riscv-fesvr | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-fesvr b/riscv-fesvr
index 6ff5489..ee2a81c 160000
--- a/riscv-fesvr
+++ b/riscv-fesvr
@@ -1 +1 @@
-Subproject commit 6ff5489612887b4bc57aad0e8821990f6d0513ac
+Subproject commit ee2a81ce890d7ea59074e2abfc0010daa103e0d7
-- 
cgit v1.1


From 8a8d7e680d48c4dc46b2ac0e8114d400d7afc4af Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@sifive.com>
Date: Fri, 31 Mar 2017 19:16:52 -0700
Subject: bump spike

---
 riscv-isa-sim | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-isa-sim b/riscv-isa-sim
index b04dfe3..f2e8eb2 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit b04dfe31de85923faf4c701ec2fcf7ff0afc6de7
+Subproject commit f2e8eb28cca2a5f49cea9f37774058718f795fdd
-- 
cgit v1.1


From cd8bc4798c38ba11118492474e96baf717c7af36 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 10 Apr 2017 21:00:46 -0700
Subject: Implement new FP encoding

https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
---
 riscv-isa-sim | 2 +-
 riscv-pk      | 2 +-
 riscv-tests   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/riscv-isa-sim b/riscv-isa-sim
index f2e8eb2..d6fce45 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit f2e8eb28cca2a5f49cea9f37774058718f795fdd
+Subproject commit d6fce459767509249311a120fddb21c844dc9b2c
diff --git a/riscv-pk b/riscv-pk
index 078ea39..8197cad 160000
--- a/riscv-pk
+++ b/riscv-pk
@@ -1 +1 @@
-Subproject commit 078ea399c6c1f2d6e8461559bf8cc1ba34ca89b6
+Subproject commit 8197cad40c5af8e4e315429be9f20aefbcc803ee
diff --git a/riscv-tests b/riscv-tests
index c066a09..2f4a658 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit c066a09ce18eb9252892d105386b40fa80242120
+Subproject commit 2f4a65844606861aa2aec43db9a49997d0e02a5f
-- 
cgit v1.1


From 1bf2c200443a20291b4f35d565c54eb96dcdf40d Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Fri, 14 Apr 2017 18:28:26 -0700
Subject: Bump pk and tests

---
 riscv-pk    | 2 +-
 riscv-tests | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-pk b/riscv-pk
index 8197cad..5f736b9 160000
--- a/riscv-pk
+++ b/riscv-pk
@@ -1 +1 @@
-Subproject commit 8197cad40c5af8e4e315429be9f20aefbcc803ee
+Subproject commit 5f736b9ab82ad19e03fc720c63f08e01a72712cc
diff --git a/riscv-tests b/riscv-tests
index 2f4a658..0d53d12 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 2f4a65844606861aa2aec43db9a49997d0e02a5f
+Subproject commit 0d53d12133bd3f7dce0e3731a5bc7dc0c1facc9d
-- 
cgit v1.1


From f4cc95748b9ac436eaf3692081e9806ca40b8934 Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@sifive.com>
Date: Mon, 1 May 2017 13:20:11 -0700
Subject: bump spike (#67)

---
 riscv-isa-sim | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-isa-sim b/riscv-isa-sim
index d6fce45..4859971 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit d6fce459767509249311a120fddb21c844dc9b2c
+Subproject commit 4859971a8879728378b0867e899b082e67737728
-- 
cgit v1.1


From 25bb7e1305d9220dddfbded12c087e8f1372b952 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 1 May 2017 14:46:06 -0700
Subject: Use ELF entry point to set spike's default start address

---
 riscv-fesvr   | 2 +-
 riscv-isa-sim | 2 +-
 riscv-opcodes | 2 +-
 riscv-pk      | 2 +-
 riscv-tests   | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/riscv-fesvr b/riscv-fesvr
index ee2a81c..6330e86 160000
--- a/riscv-fesvr
+++ b/riscv-fesvr
@@ -1 +1 @@
-Subproject commit ee2a81ce890d7ea59074e2abfc0010daa103e0d7
+Subproject commit 6330e8668092e8a9c8af97f75313261d8e39b001
diff --git a/riscv-isa-sim b/riscv-isa-sim
index 4859971..75f2a05 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit 4859971a8879728378b0867e899b082e67737728
+Subproject commit 75f2a05df9cdff6f3faba748065b3184b9f01b01
diff --git a/riscv-opcodes b/riscv-opcodes
index e4c9357..18383e7 160000
--- a/riscv-opcodes
+++ b/riscv-opcodes
@@ -1 +1 @@
-Subproject commit e4c935733f653d97913fb0418abfa89f6f3d90d2
+Subproject commit 18383e76bd447bf3d1887026791f938bf253a87b
diff --git a/riscv-pk b/riscv-pk
index 5f736b9..3aebe0d 160000
--- a/riscv-pk
+++ b/riscv-pk
@@ -1 +1 @@
-Subproject commit 5f736b9ab82ad19e03fc720c63f08e01a72712cc
+Subproject commit 3aebe0db7f08f0aeed154be9c78ea872c66fb1ec
diff --git a/riscv-tests b/riscv-tests
index 0d53d12..af832bf 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 0d53d12133bd3f7dce0e3731a5bc7dc0c1facc9d
+Subproject commit af832bf8fd7ed43631e1d1ceb66b10027419a4e6
-- 
cgit v1.1


From de3f9239356b6486552831a6605baa07b39348bd Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt <palmer@dabbelt.com>
Date: Tue, 18 Apr 2017 16:16:09 -0700
Subject: Add OpenOCD

This is required to run the debug tests.
---
 .gitmodules         | 3 +++
 .travis.yml         | 5 +++++
 build-rv32ima.sh    | 1 +
 build.common        | 8 ++++++++
 build.sh            | 1 +
 riscv-gnu-toolchain | 2 +-
 riscv-openocd       | 1 +
 7 files changed, 20 insertions(+), 1 deletion(-)
 create mode 160000 riscv-openocd

diff --git a/.gitmodules b/.gitmodules
index 2c44816..0ea42ca 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -19,3 +19,6 @@
 [submodule "riscv-gnu-toolchain"]
 	path = riscv-gnu-toolchain
 	url = https://github.com/riscv/riscv-gnu-toolchain.git
+[submodule "riscv-openocd"]
+	path = riscv-openocd
+	url = https://github.com/riscv/riscv-openocd.git
diff --git a/.travis.yml b/.travis.yml
index 9ade992..3100a4b 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -23,6 +23,7 @@ addons:
       - flex
       - texinfo
       - python-pexpect
+      - libusb-1.0-0-dev
 
 env:
   global:
@@ -37,6 +38,10 @@ before_install:
   - cd riscv-tests
   - git submodule update --init
   - cd ..
+  # openocd also needs submodules
+  - cd riscv-openocd
+  - git submodule update --init
+  - cd ..
   # actually use new gcc
   - export CXX=g++-4.8 CC=gcc-4.8
 
diff --git a/build-rv32ima.sh b/build-rv32ima.sh
index 65e93ae..eaa0bb8 100755
--- a/build-rv32ima.sh
+++ b/build-rv32ima.sh
@@ -11,5 +11,6 @@ build_project riscv-fesvr --prefix=$RISCV
 build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV --with-isa=rv32ima
 build_project riscv-gnu-toolchain --prefix=$RISCV --with-arch=rv32ima --with-abi=ilp32
 CC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv32-unknown-elf
+build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang
 
 echo -e "\\nRISC-V Toolchain installation completed!"
diff --git a/build.common b/build.common
index 3b6a1c4..fadf6ef 100644
--- a/build.common
+++ b/build.common
@@ -24,6 +24,14 @@ function build_project {
     echo "Removing existing $PROJECT/build directory"
     rm -rf "$PROJECT/build"
   fi
+  if [ ! -e "$PROJECT/configure" ]
+  then
+    (
+      cd "$PROJECT"
+      find . -iname configure.ac | sed s/configure.ac/m4/ | xargs mkdir -p
+      autoreconf -i
+    )
+  fi
   mkdir -p "$PROJECT/build"
   cd "$PROJECT/build"
   echo "Configuring project $PROJECT"
diff --git a/build.sh b/build.sh
index ec5f003..1563b7f 100755
--- a/build.sh
+++ b/build.sh
@@ -7,6 +7,7 @@
 
 echo "Starting RISC-V Toolchain build process"
 
+build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang
 build_project riscv-fesvr --prefix=$RISCV
 build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV
 build_project riscv-gnu-toolchain --prefix=$RISCV
diff --git a/riscv-gnu-toolchain b/riscv-gnu-toolchain
index 8b16c61..9f1f197 160000
--- a/riscv-gnu-toolchain
+++ b/riscv-gnu-toolchain
@@ -1 +1 @@
-Subproject commit 8b16c6123d3dc9642ceeaa6ad371f494d5970873
+Subproject commit 9f1f1971208d898705cb19e353e3da28c9f8c4a0
diff --git a/riscv-openocd b/riscv-openocd
new file mode 160000
index 0000000..ba3a569
--- /dev/null
+++ b/riscv-openocd
@@ -0,0 +1 @@
+Subproject commit ba3a56937bc921a72b672d666a60ea4292cff449
-- 
cgit v1.1


From d8311cf84dfed738e101d9cd98417f9da83920d5 Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt <palmer@dabbelt.com>
Date: Wed, 10 May 2017 13:46:29 -0700
Subject: Bump riscv-gnu-toolchain

This contains a handful of fixes, the most important of which is a PIC
signess fix that makes -mcmodel=medany work correctly.
---
 riscv-gnu-toolchain | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-gnu-toolchain b/riscv-gnu-toolchain
index 9f1f197..8b464a8 160000
--- a/riscv-gnu-toolchain
+++ b/riscv-gnu-toolchain
@@ -1 +1 @@
-Subproject commit 9f1f1971208d898705cb19e353e3da28c9f8c4a0
+Subproject commit 8b464a814a32671d8315eba5fcab10d0efc85081
-- 
cgit v1.1


From d98aabcc66a130a2de0d52cada93c078a5c26bf0 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Sun, 14 May 2017 19:44:40 -0700
Subject: bump debug-v0.13 to current priv-1.10 of tools

---
 riscv-tests | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-tests b/riscv-tests
index af832bf..201fc77 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit af832bf8fd7ed43631e1d1ceb66b10027419a4e6
+Subproject commit 201fc773aef7f93107cbe098b9531ba6e18cd913
-- 
cgit v1.1


From 6c4521092d0d77575f46bedc5d29ab9166828d0e Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Mon, 15 May 2017 00:56:38 -0700
Subject: bump debug tests

---
 riscv-tests | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-tests b/riscv-tests
index 201fc77..46fdf49 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 201fc773aef7f93107cbe098b9531ba6e18cd913
+Subproject commit 46fdf4920da71f3f8690349d72fe6a516fd97735
-- 
cgit v1.1


From 7b16d80ff33835df70a452bcd4264e1efcd2eeec Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Mon, 15 May 2017 10:20:10 -0700
Subject: bump debug tests

---
 riscv-tests | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-tests b/riscv-tests
index 46fdf49..f7095ba 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 46fdf4920da71f3f8690349d72fe6a516fd97735
+Subproject commit f7095baa9d9a23ad096084380a9457730ea2ac68
-- 
cgit v1.1


From f93c34cc53477c0704ce60e292c4659a0580e275 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Mon, 15 May 2017 10:23:16 -0700
Subject: bump openocd

---
 riscv-openocd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-openocd b/riscv-openocd
index ba3a569..bcf2a16 160000
--- a/riscv-openocd
+++ b/riscv-openocd
@@ -1 +1 @@
-Subproject commit ba3a56937bc921a72b672d666a60ea4292cff449
+Subproject commit bcf2a16b0d0d186fdfb371ff4e8009251626ee22
-- 
cgit v1.1


From eb4221bf6d753ef74852f45ef53668ee750864fd Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Mon, 15 May 2017 10:26:42 -0700
Subject: bump spike to allow testing debug-check

---
 riscv-isa-sim | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-isa-sim b/riscv-isa-sim
index 75f2a05..a5c5d0c 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit 75f2a05df9cdff6f3faba748065b3184b9f01b01
+Subproject commit a5c5d0ccf2ac85452107af473016418626ad969b
-- 
cgit v1.1


From 72500898ed3dd6ca4b6ff73022438ba106d3eb53 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Mon, 15 May 2017 10:38:12 -0700
Subject: riscv-openocd: Also build with jtag-vpi as this is used to run
 against simulators.

---
 build.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/build.sh b/build.sh
index 1563b7f..eb9cf6a 100755
--- a/build.sh
+++ b/build.sh
@@ -7,7 +7,7 @@
 
 echo "Starting RISC-V Toolchain build process"
 
-build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang
+build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi
 build_project riscv-fesvr --prefix=$RISCV
 build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV
 build_project riscv-gnu-toolchain --prefix=$RISCV
-- 
cgit v1.1


From 60e1d336bfbb9ab7b8a8d4331d11dc43268ed29a Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Mon, 15 May 2017 13:35:38 -0700
Subject: bump openocd to remove some compile warnings

---
 riscv-openocd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-openocd b/riscv-openocd
index bcf2a16..234ab5f 160000
--- a/riscv-openocd
+++ b/riscv-openocd
@@ -1 +1 @@
-Subproject commit bcf2a16b0d0d186fdfb371ff4e8009251626ee22
+Subproject commit 234ab5fb0b783aaf84008852e19bc1f684847237
-- 
cgit v1.1


From 66e463d14ebd95ccbb8e1882a172e7e623c32a4d Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Mon, 15 May 2017 13:47:05 -0700
Subject: bump openocd to pick up build fixes on master

---
 riscv-openocd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-openocd b/riscv-openocd
index 234ab5f..8252b9d 160000
--- a/riscv-openocd
+++ b/riscv-openocd
@@ -1 +1 @@
-Subproject commit 234ab5fb0b783aaf84008852e19bc1f684847237
+Subproject commit 8252b9d36cd327a06c3a096ee1175a891d71eb11
-- 
cgit v1.1


From 10495353eaf3287bc1296051415ab318fd41461f Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Tue, 16 May 2017 10:09:08 -0700
Subject: bump tests for cleaner debug configs

---
 riscv-tests | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-tests b/riscv-tests
index f7095ba..8dc1490 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit f7095baa9d9a23ad096084380a9457730ea2ac68
+Subproject commit 8dc1490a5a86549a89cc8276477a158da68840b5
-- 
cgit v1.1


From f60166c1b31f66458e2ffc48425c4bccfffdb0ee Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt <palmer@dabbelt.com>
Date: Tue, 16 May 2017 13:51:15 -0700
Subject: Bump all the submodules from the debug-0.13 -> priv-1.10 merge

This also makes Travis run the debug tests.
---
 .travis.yml         | 5 +++--
 riscv-gnu-toolchain | 2 +-
 riscv-isa-sim       | 2 +-
 riscv-opcodes       | 2 +-
 riscv-openocd       | 2 +-
 riscv-pk            | 2 +-
 riscv-tests         | 2 +-
 7 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 3100a4b..2c65b48 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -24,6 +24,7 @@ addons:
       - texinfo
       - python-pexpect
       - libusb-1.0-0-dev
+      - device-tree-compiler
 
 env:
   global:
@@ -50,5 +51,5 @@ install: travis_wait
 
 script:
   - ./build.sh
-  #- cd riscv-tests/build
-  #- make debug-check
+  - cd riscv-tests/build
+  - make debug-check || (tail debug/*.log; exit 1)
diff --git a/riscv-gnu-toolchain b/riscv-gnu-toolchain
index 8b464a8..a71fc53 160000
--- a/riscv-gnu-toolchain
+++ b/riscv-gnu-toolchain
@@ -1 +1 @@
-Subproject commit 8b464a814a32671d8315eba5fcab10d0efc85081
+Subproject commit a71fc539850f8dacf232fc580743b946c376014b
diff --git a/riscv-isa-sim b/riscv-isa-sim
index a5c5d0c..a1f754b 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit a5c5d0ccf2ac85452107af473016418626ad969b
+Subproject commit a1f754b2f0ec5fe72c86d6916d7c603e7727e68e
diff --git a/riscv-opcodes b/riscv-opcodes
index 18383e7..f8bab12 160000
--- a/riscv-opcodes
+++ b/riscv-opcodes
@@ -1 +1 @@
-Subproject commit 18383e76bd447bf3d1887026791f938bf253a87b
+Subproject commit f8bab126082ce7fcd9e91ad54918bd1cf913da3b
diff --git a/riscv-openocd b/riscv-openocd
index 8252b9d..c431c0e 160000
--- a/riscv-openocd
+++ b/riscv-openocd
@@ -1 +1 @@
-Subproject commit 8252b9d36cd327a06c3a096ee1175a891d71eb11
+Subproject commit c431c0eb251bf6d02959a6f55be3baba04552b5d
diff --git a/riscv-pk b/riscv-pk
index 3aebe0d..66701f8 160000
--- a/riscv-pk
+++ b/riscv-pk
@@ -1 +1 @@
-Subproject commit 3aebe0db7f08f0aeed154be9c78ea872c66fb1ec
+Subproject commit 66701f82f88d08d3700d8b0bc5d5306abfd0044f
diff --git a/riscv-tests b/riscv-tests
index 8dc1490..4c8a335 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 8dc1490a5a86549a89cc8276477a158da68840b5
+Subproject commit 4c8a335f6aabd6c05577aceb31eb9b16142eb67c
-- 
cgit v1.1


From 625e7e4fd0e44fa01b30e176a7e6e0b96bb206eb Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt <palmer@dabbelt.com>
Date: Wed, 17 May 2017 09:59:47 -0700
Subject: Try using 2 instead of 3 threads

---
 .travis.yml | 2 +-
 riscv-tests | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 2c65b48..f5d0ede 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -29,7 +29,7 @@ addons:
 env:
   global:
     - RISCV="/home/travis/riscv_install"
-    - MAKEFLAGS="-j3"
+    - MAKEFLAGS="-j2"
     - PATH="/home/travis/riscv_install/bin:$PATH"
 
 before_install:
diff --git a/riscv-tests b/riscv-tests
index 4c8a335..2b0193d 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 4c8a335f6aabd6c05577aceb31eb9b16142eb67c
+Subproject commit 2b0193de9f7cb43d3b3c519fe8eff497ea738598
-- 
cgit v1.1