From 0e98addfd00372800152eedd723939a84a794ea7 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 9 Nov 2017 19:29:01 -0800
Subject: bump tests for rv64mi-p-ecall fix

---
 riscv-isa-sim | 2 +-
 riscv-tests   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-isa-sim b/riscv-isa-sim
index 3b1e9ab..f5bdc2e 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit 3b1e9ab7522b3b20cde6bd8d9f2b28222463cf1b
+Subproject commit f5bdc2e34299e3721c9319ba92dc72149f6af8a2
diff --git a/riscv-tests b/riscv-tests
index 82da8bc..d9b4071 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit 82da8bccd1903c766f3a29f2b6a671cc059f0bce
+Subproject commit d9b4071ea4a9a2fe84a51443250184f51e931ac2
-- 
cgit v1.1