From 0981f000a1a2033b56d1a3aadf7a859eaeca5934 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 5 Sep 2018 09:35:12 -0700
Subject: debug: bump Spike to support custom registers

---
 riscv-isa-sim | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv-isa-sim b/riscv-isa-sim
index b6ec196..aff796d 160000
--- a/riscv-isa-sim
+++ b/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit b6ec196e9efe33d29d0c9fb80202737719c7730f
+Subproject commit aff796dbf6db66a2df53b0ca270382f0ce02da74
-- 
cgit v1.1