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path: root/riscv-isa-sim
AgeCommit message (Expand)AuthorFilesLines
2015-11-25Use MMIO for device discoveryAndrew Waterman1-0/+0
2015-09-28bump submodulesScott Beamer1-0/+0
2015-08-18Upgrade to privileged architecture v1.7, sans qemuAndrew Waterman1-0/+0
2015-02-17sync up riscv-toolsYunsup Lee1-0/+0
2015-01-20update all reposAndrew Waterman1-0/+0
2015-01-04update all reposAndrew Waterman1-0/+0
2014-12-03New ABI/toolAndrew Waterman1-0/+0
2014-10-24push isa-sim,opcodes,pk,testsYunsup Lee1-0/+0
2014-10-12bump submodule versionsScott Beamer1-0/+0
2014-08-21bump submodule versionsScott Beamer1-0/+0
2014-07-30bump submodulesSagar Karandikar1-0/+0
2014-04-25Various toolchain fixes/improvementsAndrew Waterman1-0/+0
2014-04-07Update riscv-opcodes. Other correspondent projects made consistent.Stephen Twigg1-0/+0
2014-03-11New FP encodingAndrew Waterman1-0/+0
2014-03-08Add fclass.{s|d} instructionsAndrew Waterman1-0/+0
2014-03-02sync up gcc,isa-sim,opcodes,pk,testsYunsup Lee1-0/+0
2014-02-25add extensions option to riscv-dis for better disassemblyYunsup Lee1-0/+0
2014-02-14Renumber uarch CSRs into custom CSR spaceAndrew Waterman1-0/+0
2014-02-10Revert to old AUIPC definitionAndrew Waterman1-0/+0
2014-02-06push gcc,spike,pk,testsYunsup Lee1-0/+0
2014-02-03Remove vsetprec and add vfmsv, vfmvvQuan Nguyen1-0/+0
2014-01-31Fix Darwin buildAndrew Waterman1-0/+0
2014-01-28Fix some bugs related to dynamic linkingAndrew Waterman1-0/+0
2014-01-26Build and use dynamic librariesAndrew Waterman1-0/+0
2014-01-21Generate CAUSE numbers from riscv-opcodes; add CSR testAndrew Waterman1-0/+0
2014-01-20Catch up to recent toolchain changesQuan Nguyen1-0/+0
2013-11-29Add vsetprec instruction prototypeQuan Nguyen1-0/+0
2013-11-26Create confprec tool branchQuan Nguyen1-0/+0
2013-11-05push isa-sim,pk,testsYunsup Lee1-0/+0
2013-10-28push isa-simYunsup Lee1-0/+0
2013-10-21push isa-simYunsup Lee1-0/+0
2013-10-18push isa-sim,opcodes,testsYunsup Lee1-0/+0
2013-10-18push isa-sim,testsYunsup Lee1-0/+0
2013-10-18push isa-simYunsup Lee1-0/+0
2013-10-17push gcc,isa-sim,opcodes,testsYunsup Lee1-0/+0
2013-10-17push gcc,isa-sim,opcodes,testsYunsup Lee1-0/+0
2013-10-10push gcc,isa-sim,opcodes,pk,testsYunsup Lee1-0/+0
2013-09-22Hammer spike (fix issue with accelerator instructions)Stephen Twigg1-0/+0
2013-09-21New ISA encodingAndrew Waterman1-0/+0
2013-06-10Fix Darwin build againAndrew Waterman1-0/+0
2013-05-15push riscv-isa-simYunsup Lee1-0/+0
2013-05-13push riscv-isa-sim,riscv-testsYunsup Lee1-0/+0
2013-04-29use new gcc configure script; build isa testsAndrew Waterman1-0/+0
2013-04-29push riscv-isa-simYunsup Lee1-0/+0
2013-04-24push riscv-gcc,riscv-isa-simYunsup Lee1-0/+0
2013-04-22push riscv-isa-simYunsup Lee1-0/+0
2013-04-19push riscv-fesvr,riscv-gcc,riscv-isa-sim,riscv-opcodes,riscv-pkYunsup Lee1-0/+0
2013-03-19push riscv-gcc,riscv-isa-sim,riscv-pkYunsup Lee1-0/+0
2013-02-13add cache simulators to isa simulatorAndrew Waterman1-0/+0
2013-01-25push riscv-isa-simAndrew Waterman1-0/+0
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