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| author | Jiongjia Lu <dev@avimit.in> | 2024-12-24 08:26:19 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-23 16:26:19 -0800 |
| commit | 81721c126d7dd7335829948b4a19070546e465d6 (patch) | |
| tree | 1bf26a83a721235f3b03810af30a0efccae2746b | |
| parent | 1c577dc7c7d6aee27b8d5cb0e2e87c8473e3ad12 (diff) | |
| download | env-master.zip env-master.tar.gz env-master.tar.bz2 | |
The default RVTEST_VECTOR_ENABLE macro always write fcsr and cause tests
failure on vector processor without float support. This commit add new
macro to init only vector related register.
Signed-off-by: Avimitin <dev@avimit.in>
| -rw-r--r-- | p/riscv_test.h | 15 | ||||
| -rw-r--r-- | v/riscv_test.h | 4 |
2 files changed, 19 insertions, 0 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index 7bf35cf..3d4637a 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -23,6 +23,11 @@ RVTEST_VECTOR_ENABLE; \ .endm +#define RVTEST_RV64UVX \ + .macro init; \ + RVTEST_ZVE32X_ENABLE; \ + .endm + #define RVTEST_RV32U \ .macro init; \ .endm @@ -37,6 +42,11 @@ RVTEST_VECTOR_ENABLE; \ .endm +#define RVTEST_RV32UVX \ + .macro init; \ + RVTEST_ZVE32X_ENABLE; \ + .endm + #define RVTEST_RV64M \ .macro init; \ RVTEST_ENABLE_MACHINE; \ @@ -152,6 +162,11 @@ csrwi fcsr, 0; \ csrwi vcsr, 0; +#define RVTEST_ZVE32X_ENABLE \ + li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)); \ + csrs mstatus, a0; \ + csrwi vcsr, 0; + #define RISCV_MULTICORE_DISABLE \ csrr a0, mhartid; \ 1: bnez a0, 1b diff --git a/v/riscv_test.h b/v/riscv_test.h index f56c022..e935376 100644 --- a/v/riscv_test.h +++ b/v/riscv_test.h @@ -17,6 +17,10 @@ csrwi fcsr, 0; \ csrwi vcsr, 0; +#undef RVTEST_ZVE32X_ENABLE +#define RVTEST_ZVE32X_ENABLE \ + csrwi vcsr, 0; + #undef RVTEST_CODE_BEGIN #define RVTEST_CODE_BEGIN \ .text; \ |