1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
|
# See LICENSE for license details.
#*****************************************************************************
# ma_fetch.S
#-----------------------------------------------------------------------------
#
# Test misaligned fetch trap.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64S
RVTEST_CODE_BEGIN
#ifdef __MACHINE_MODE
#define sscratch mscratch
#define sstatus mstatus
#define scause mcause
#define sbadaddr mbadaddr
#define sepc mepc
#define sret mret
#define stvec_handler mtvec_handler
#endif
.option norvc
# Without RVC, the jalr should trap, and the handler will skip ahead.
# With RVC, the jalr should not trap, and "j fail" should get skipped.
li TESTNUM, 2
li t1, 0
la t0, 1f
jalr t1, t0, 2
1:
.option rvc
c.j 1f
c.j 2f
.option norvc
1:
j fail
2:
// This test should pass, since JALR ignores the target LSB
li TESTNUM, 3
la t0, 1f
jalr t1, t0, 1
1:
j 1f
j fail
1:
li TESTNUM, 4
li t1, 0
la t0, 1f
jalr t1, t0, 3
1:
.option rvc
c.j 1f
c.j 2f
.option norvc
1:
j fail
2:
# Like test 2, but with jal instead of jalr.
li TESTNUM, 5
li t1, 0
la t0, 1f
jal t1, 2f
1:
.option rvc
c.j 1f
2:
c.j 2f
.option norvc
1:
j fail
2:
# Like test 2, but with a taken branch instead of jalr.
li TESTNUM, 6
li t1, 0
la t0, 1f
beqz x0, 2f
1:
.option rvc
c.j 1f
2:
c.j 2f
.option norvc
1:
j fail
2:
# Not-taken branches should not trap, even without RVC.
li TESTNUM, 7
bnez x0, 1f
j 2f
.option rvc
c.j 1f
1:
c.j 1f
.option norvc
1:
j fail
2:
j pass
TEST_PASSFAIL
.align 2
.global stvec_handler
stvec_handler:
# tests 2, 4, 5, and 6 should trap
li a0, 2
beq TESTNUM, a0, 1f
li a0, 4
beq TESTNUM, a0, 1f
li a0, 5
beq TESTNUM, a0, 1f
li a0, 6
beq TESTNUM, a0, 1f
j fail
1:
# verify that return address was not written
bnez t1, fail
# verify trap cause
li a1, CAUSE_MISALIGNED_FETCH
csrr a0, scause
bne a0, a1, fail
# verify that epc == &jalr (== t0 - 4)
csrr a1, sepc
addi a1, a1, 4
bne t0, a1, fail
# verify that badaddr == 0 or badaddr == t0+2.
csrr a0, sbadaddr
beqz a0, 1f
addi a0, a0, -2
bne a0, t0, fail
1:
addi a1, a1, 12
csrw sepc, a1
sret
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
