From d5fb1309c80bf57cb33e53b7fa6010fe6a374062 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 22 Jul 2016 11:25:52 -0700
Subject: Move dirty bit test to rv64si directory

Not sure this is quite right, since the test technically runs in M-mode.

Also, remove unused rdnpc/example tests.
---
 isa/rv64si/Makefrag |  1 +
 isa/rv64si/dirty.S  | 93 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 94 insertions(+)
 create mode 100644 isa/rv64si/dirty.S

(limited to 'isa/rv64si')

diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag
index 076ea59..c0dbce8 100644
--- a/isa/rv64si/Makefrag
+++ b/isa/rv64si/Makefrag
@@ -4,6 +4,7 @@
 
 rv64si_sc_tests = \
 	csr \
+	dirty \
 	ma_fetch \
 	scall \
 	wfi \
diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S
new file mode 100644
index 0000000..0314cf5
--- /dev/null
+++ b/isa/rv64si/dirty.S
@@ -0,0 +1,93 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# dirty.S
+#-----------------------------------------------------------------------------
+#
+# Test VM referenced and dirty bits.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  # Turn on VM with superpage identity mapping
+  la a1, page_table_1
+  srl a1, a1, RISCV_PGSHIFT
+  la a2, page_table_2
+  srl a2, a2, RISCV_PGSHIFT
+  csrw sptbr, a1
+  sfence.vm
+  li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
+  csrs mstatus, a1
+  la a1, 1f - DRAM_BASE
+  csrw mepc, a1
+  la a1, stvec_handler - DRAM_BASE
+  csrw stvec, a1
+  mret
+1:
+
+  # Try a faulting store to make sure dirty bit is not set
+  li TESTNUM, 2
+  li t0, 1
+  sw t0, dummy, t1
+
+  # Load new page table
+  li TESTNUM, 3
+  csrw sptbr, a2
+  sfence.vm
+
+  # Try a non-faulting store to make sure dirty bit is set
+  sw t0, dummy, t1
+
+  # Make sure R and D bits are set
+  lw t0, page_table_2
+  li t1, PTE_A | PTE_D
+  and t0, t0, t1
+  bne t0, t1, die
+  
+  RVTEST_PASS
+
+  TEST_PASSFAIL
+
+  .align 2
+stvec_handler:
+  csrr t0, scause
+  li t1, 2
+  bne TESTNUM, t1, 1f
+  # Make sure R bit is set
+  lw t0, page_table_1
+  li t1, PTE_A
+  and t0, t0, t1
+  bne t0, t1, die
+
+  # Make sure D bit is clear
+  lw t0, page_table_1
+  li t1, PTE_D
+  and t0, t0, t1
+  beq t0, t1, die
+
+  csrr t0, sepc
+  add t0, t0, 4
+  csrw sepc, t0
+  sret
+
+die:
+  RVTEST_FAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+.align 12
+page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X
+dummy: .dword 0
+.align 12
+page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W
+
+RVTEST_DATA_END
-- 
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