From 94a29da063eecda0f37f9f6a97ffb39a47825b35 Mon Sep 17 00:00:00 2001
From: cgsfv <cgsfv@users.noreply.github.com>
Date: Tue, 13 Nov 2018 11:56:10 +0100
Subject: Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fix

---
 debug/gdbserver.py                   | 52 ++++++++++++++++++++++++++++++++++++
 debug/targets.py                     |  3 +++
 debug/targets/SiFive/Freedom/E300.py |  3 ++-
 debug/targets/SiFive/Freedom/U500.py |  3 ++-
 4 files changed, 59 insertions(+), 2 deletions(-)

(limited to 'debug')

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index b6e7cf9..05a57cb 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -232,6 +232,58 @@ class MemTest64(SimpleMemoryTest):
 #            assertEqual(e.address, 0xdeadbeef)
 #        self.gdb.p("*((int*)0x%x)=6874742" % self.hart.ram)
 
+class MemTestBlockReadInvalid(GdbTest):
+    zero_values = "00 00 00 00 00 00 00 00"
+    real_values = "EF BE AD DE 78 56 34 12"
+
+    def early_applicable(self):
+        return self.target.uses_dtm_version_013
+
+    def test(self):
+        self.gdb.p("*((int*)0x%x) = 0xdeadbeef" % (self.hart.ram + 0))
+        self.gdb.p("*((int*)0x%x) = 0x12345678" % (self.hart.ram + 4))
+
+        # read before start of memory
+        self.memory_test(self.hart.ram - 8,
+                         self.hart.ram,
+                         self.zero_values)
+
+        # read across start of memory
+        self.memory_test(self.hart.ram - 8,
+                         self.hart.ram + 8,
+                         self.zero_values + " " + self.real_values)
+
+        # read after start of memory
+        self.memory_test(self.hart.ram,
+                         self.hart.ram + 8,
+                         self.real_values)
+
+        self.gdb.p("*((int*)0x%x) = 0xdeadbeef" % (self.hart.ram + self.hart.ram_size - 8))
+        self.gdb.p("*((int*)0x%x) = 0x12345678" % (self.hart.ram + self.hart.ram_size - 4))
+
+        # read before end of memory
+        self.memory_test(self.hart.ram + self.hart.ram_size - 8,
+                         self.hart.ram + self.hart.ram_size,
+                         self.real_values)
+
+        # read across end of memory
+        self.memory_test(self.hart.ram + self.hart.ram_size - 8,
+                         self.hart.ram + self.hart.ram_size + 8,
+                         self.real_values + " " + self.zero_values)
+
+        # read after end of memory
+        self.memory_test(self.hart.ram + self.hart.ram_size,
+                         self.hart.ram + self.hart.ram_size + 8,
+                         self.zero_values)
+
+    def memory_test(self, start_addr, end_addr, expected_values):
+        dump = tempfile.NamedTemporaryFile(suffix=".simdata")
+        self.gdb.command("dump verilog memory %s 0x%x 0x%x" % (dump.name, start_addr, end_addr))
+        self.gdb.command("shell cat %s" % dump.name)
+        line = dump.readline()
+        line = dump.readline()
+        assertEqual(line.strip(' \t\n\r'), expected_values)
+
 class MemTestBlock(GdbTest):
     length = 1024
     line_length = 16
diff --git a/debug/targets.py b/debug/targets.py
index 63994db..b5b7f7b 100644
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -79,6 +79,9 @@ class Target(object):
     # hardware will every do that.
     implements_custom_test = False
 
+    # Target uses the DTM Version 0.13 for memory accesses
+    uses_dtm_version_013 = False
+
     # Internal variables:
     directory = None
     temporary_files = []
diff --git a/debug/targets/SiFive/Freedom/E300.py b/debug/targets/SiFive/Freedom/E300.py
index 170de40..4062e3d 100644
--- a/debug/targets/SiFive/Freedom/E300.py
+++ b/debug/targets/SiFive/Freedom/E300.py
@@ -3,10 +3,11 @@ import targets
 class E300Hart(targets.Hart):
     xlen = 32
     ram = 0x80000000
-    ram_size = 256 * 1024 * 1024
+    ram_size = 64 * 1024
     instruction_hardware_breakpoint_count = 2
     link_script_path = "Freedom.lds"
 
 class E300(targets.Target):
     openocd_config_path = "Freedom.cfg"
     harts = [E300Hart()]
+    uses_dtm_version_013 = True
diff --git a/debug/targets/SiFive/Freedom/U500.py b/debug/targets/SiFive/Freedom/U500.py
index 6da3ac5..83a1343 100644
--- a/debug/targets/SiFive/Freedom/U500.py
+++ b/debug/targets/SiFive/Freedom/U500.py
@@ -3,10 +3,11 @@ import targets
 class U500Hart(targets.Hart):
     xlen = 64
     ram = 0x80000000
-    ram_size = 16 * 1024
+    ram_size = 64 * 1024
     instruction_hardware_breakpoint_count = 2
     link_script_path = "Freedom.lds"
 
 class U500(targets.Target):
     openocd_config_path = "Freedom.cfg"
     harts = [U500Hart()]
+    uses_dtm_version_013 = True
-- 
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