From f68760e7e0295a03ccf3147571f4254cc352e4fc Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 6 Aug 2020 08:50:43 -0700 Subject: Add enable_rtos_riscv (#288) This is now required to use `-rtos riscv`. Addresses the aside mentioned in #287. --- debug/targets/RISC-V/spike-rtos.cfg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg index 7cd1c3f..395a9f8 100644 --- a/debug/targets/RISC-V/spike-rtos.cfg +++ b/debug/targets/RISC-V/spike-rtos.cfg @@ -8,6 +8,8 @@ remote_bitbang_port $::env(REMOTE_BITBANG_PORT) set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 +enable_rtos_riscv + set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv -- cgit v1.1