From d8177046a0809eb29241641c040eff81ead8a8de Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Mon, 8 Apr 2019 10:59:55 -0700
Subject: Test lack of abstract CSR access. (#187)

---
 debug/targets/RISC-V/spike32-2-rtos.py | 2 +-
 debug/targets/RISC-V/spike32-2.py      | 3 ++-
 debug/targets/RISC-V/spike32.py        | 3 ++-
 debug/targets/RISC-V/spike64-2-rtos.py | 3 ++-
 debug/targets/RISC-V/spike64-2.py      | 2 +-
 debug/targets/RISC-V/spike64.py        | 2 +-
 debug/testlib.py                       | 7 +++++--
 7 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py
index 4b29801..3a2e8b8 100644
--- a/debug/targets/RISC-V/spike32-2-rtos.py
+++ b/debug/targets/RISC-V/spike32-2-rtos.py
@@ -12,4 +12,4 @@ class spike32_2(targets.Target):
 
     def create(self):
         return testlib.Spike(self, progbufsize=0, dmi_rti=4,
-                support_hasel=False)
+                support_hasel=False, support_abstract_csr=True)
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index 8872ad3..a6fac39 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -10,4 +10,5 @@ class spike32_2(targets.Target):
     implements_custom_test = True
 
     def create(self):
-        return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4)
+        return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4,
+                support_abstract_csr=True)
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index e633eea..6894bcf 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -17,4 +17,5 @@ class spike32(targets.Target):
 
     def create(self):
         # 64-bit FPRs on 32-bit target
-        return testlib.Spike(self, isa="RV32IMAFDC", dmi_rti=4)
+        return testlib.Spike(self, isa="RV32IMAFDC", dmi_rti=4,
+                support_abstract_csr=True)
diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py
index 3e7c221..8dee51a 100644
--- a/debug/targets/RISC-V/spike64-2-rtos.py
+++ b/debug/targets/RISC-V/spike64-2-rtos.py
@@ -11,4 +11,5 @@ class spike64_2_rtos(targets.Target):
     support_hasel = False
 
     def create(self):
-        return testlib.Spike(self, abstract_rti=30, support_hasel=False)
+        return testlib.Spike(self, abstract_rti=30, support_hasel=False,
+                support_abstract_csr=False)
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index beccae3..596098d 100644
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -12,4 +12,4 @@ class spike64_2(targets.Target):
 
     def create(self):
         return testlib.Spike(self, isa="RV64IMAFD", abstract_rti=30,
-                support_hasel=False)
+                support_hasel=False, support_abstract_csr=False)
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index fdb1282..c4c7796 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -18,4 +18,4 @@ class spike64(targets.Target):
     def create(self):
         # 32-bit FPRs only
         return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0,
-                abstract_rti=30)
+                abstract_rti=30, support_abstract_csr=True)
diff --git a/debug/testlib.py b/debug/testlib.py
index b3163c3..d0383cb 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -59,7 +59,7 @@ class Spike(object):
     # pylint: disable=too-many-instance-attributes
     def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
             isa=None, progbufsize=None, dmi_rti=None, abstract_rti=None,
-            support_hasel=True):
+            support_hasel=True, support_abstract_csr=True):
         """Launch spike. Return tuple of its process and the port it's running
         on."""
         self.process = None
@@ -67,6 +67,7 @@ class Spike(object):
         self.progbufsize = progbufsize
         self.dmi_rti = dmi_rti
         self.abstract_rti = abstract_rti
+        self.support_abstract_csr = support_abstract_csr
         self.support_hasel = support_hasel
 
         if target.harts:
@@ -135,6 +136,9 @@ class Spike(object):
         if not self.abstract_rti is None:
             cmd += ["--abstract-rti", str(self.abstract_rti)]
 
+        if not self.support_abstract_csr:
+            cmd.append("--debug-no-abstract-csr")
+
         if not self.support_hasel:
             cmd.append("--without-hasel")
 
@@ -790,7 +794,6 @@ class BaseTest(object):
             self.hart = hart
         else:
             self.hart = random.choice(target.harts)
-            self.hart = target.harts[-1]    #<<<
         self.server = None
         self.target_process = None
         self.binary = None
-- 
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