From a29522f3e4baec1a50beb01ec70d69a94ac0083c Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Fri, 23 Jun 2023 17:06:31 -0700
Subject: debug: Add support_unavailable_control property.

---
 debug/targets.py                           | 3 +++
 debug/targets/RISC-V/spike32-2-hwthread.py | 1 +
 debug/targets/RISC-V/spike32-2.py          | 1 +
 debug/targets/RISC-V/spike32.py            | 1 +
 debug/targets/RISC-V/spike64-2-hwthread.py | 1 +
 debug/targets/RISC-V/spike64-2-rtos.py     | 1 +
 debug/targets/RISC-V/spike64-2.py          | 1 +
 debug/targets/RISC-V/spike64.py            | 1 +
 8 files changed, 10 insertions(+)

diff --git a/debug/targets.py b/debug/targets.py
index 1952749..3f63e79 100644
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -129,6 +129,9 @@ class Target:
     # in https://github.com/FreeRTOS/FreeRTOS.
     freertos_binary = None
 
+    # Supports controlling hart availability through DMCUSTOM.
+    support_unavailable_control = False
+
     # Internal variables:
     directory = None
     temporary_files = []
diff --git a/debug/targets/RISC-V/spike32-2-hwthread.py b/debug/targets/RISC-V/spike32-2-hwthread.py
index 3a24269..b617be2 100644
--- a/debug/targets/RISC-V/spike32-2-hwthread.py
+++ b/debug/targets/RISC-V/spike32-2-hwthread.py
@@ -10,6 +10,7 @@ class spike32_2(targets.Target):
     timeout_sec = 5
     implements_custom_test = True
     support_memory_sampling = False # not supported without sba
+    support_unavailable_control = True
 
     def create(self):
         return testlib.Spike(self, isa="RV32IMAFDV", support_hasel=True,
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index 6a5a839..1d0cc48 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -9,6 +9,7 @@ class spike32_2(targets.Target):
     openocd_config_path = "spike-2.cfg"
     timeout_sec = 30
     implements_custom_test = True
+    support_unavailable_control = True
 
     def create(self):
         return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4,
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index 0d67ebd..f0afd88 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -17,6 +17,7 @@ class spike32(targets.Target):
     implements_custom_test = True
     support_memory_sampling = False # Needs SBA
     freertos_binary = "bin/RTOSDemo32.axf"
+    support_unavailable_control = True
 
     def create(self):
         # 64-bit FPRs on 32-bit target
diff --git a/debug/targets/RISC-V/spike64-2-hwthread.py b/debug/targets/RISC-V/spike64-2-hwthread.py
index 1ac184a..d1d2bf7 100644
--- a/debug/targets/RISC-V/spike64-2-hwthread.py
+++ b/debug/targets/RISC-V/spike64-2-hwthread.py
@@ -13,6 +13,7 @@ class spike64_2(targets.Target):
     implements_custom_test = True
     support_hasel = False
     support_memory_sampling = False # Needs SBA
+    support_unavailable_control = True
 
     def create(self):
         return testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30,
diff --git a/debug/targets/RISC-V/spike64-2-rtos.py b/debug/targets/RISC-V/spike64-2-rtos.py
index 33c1ff2..f4de8b8 100644
--- a/debug/targets/RISC-V/spike64-2-rtos.py
+++ b/debug/targets/RISC-V/spike64-2-rtos.py
@@ -13,6 +13,7 @@ class spike64_2_rtos(targets.Target):
     test_semihosting = False
     support_manual_hwbp = False # not supported with `-rtos riscv`
     support_memory_sampling = False # not supported with `-rtos riscv`
+    support_unavailable_control = True
 
     def create(self):
         return testlib.Spike(self, abstract_rti=30, support_hasel=False,
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
index 48326ad..e4c7524 100644
--- a/debug/targets/RISC-V/spike64-2.py
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -10,6 +10,7 @@ class spike64_2(targets.Target):
     timeout_sec = 5
     implements_custom_test = True
     support_memory_sampling = False # Needs SBA
+    support_unavailable_control = True
 
     def create(self):
         return testlib.Spike(self)
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index 79176c2..8f5ba4f 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -17,6 +17,7 @@ class spike64(targets.Target):
     timeout_sec = 30
     implements_custom_test = True
     freertos_binary = "bin/RTOSDemo64.axf"
+    support_unavailable_control = True
 
     def create(self):
         # 32-bit FPRs only
-- 
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