From 5e62d380c54524d8916573aa3397270f457e4901 Mon Sep 17 00:00:00 2001
From: Marek Vrbka <133884222+MarekVCodasip@users.noreply.github.com>
Date: Thu, 13 Jul 2023 17:46:09 +0200
Subject: Add an exclude list for known failing Hifive1 tests (#485)

* Add an exclude list for known failing Hifive1 tests

This commit adds a list of known failing tests based on: https://github.com/riscv/riscv-openocd/issues/869#issue-1769176709

* Fix name of the HiFive1 flash target

Signed-off-by: Marek Vrbka <133884222+MarekVCodasip@users.noreply.github.com>

---------

Signed-off-by: Marek Vrbka <133884222+MarekVCodasip@users.noreply.github.com>
---
 debug/hifive1_excludes.yaml | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 debug/hifive1_excludes.yaml

diff --git a/debug/hifive1_excludes.yaml b/debug/hifive1_excludes.yaml
new file mode 100644
index 0000000..f9391ee
--- /dev/null
+++ b/debug/hifive1_excludes.yaml
@@ -0,0 +1,28 @@
+# Below are known failing tests on riscv-openocd on HiFive1 board, rev. A01.
+# This board uses the legacy debug spec v 0.11.
+
+# Tested on Jun-26-2023.
+# riscv-openocd commit: a45589d60aa6864475fddcded885c8ff47d50be1
+# riscv-tests commit: 7b52ba3b7167acb4d8b38f4d4633112b4699cb26
+
+all:
+  - EtriggerTest
+  - IcountTest
+  - InstantHaltTest
+  - ItriggerTest
+  - MemorySampleMixed
+  - MemorySampleSingle
+  - MemTestReadInvalid
+  - RepeatReadTest
+  - Semihosting
+  - SemihostingFileio
+
+HiFive1Flash:
+  - DebugBreakpoint
+  - DebugExit
+  - DebugFunctionCall
+  - Hwbp1
+  - Hwbp2
+  - Registers
+  - TooManyHwbp
+  - UserInterrupt
-- 
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