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2022-06-07Test misaligned loads.Tim Newsome8-0/+160
Cover lh, lw, and ld (only on rv64).
2022-06-07Set TESTNUM before executing code.Tim Newsome3-6/+4
Tests that might cause a trap during their code need TESTNUM (gp) set so the trap handler can correctly identify which test is running, and also report that to the user in case the test fails. Fix up shamt.S and csr.S to handle the new behavior.
2022-06-06Revert unaligned tests.Tim Newsome3-51/+1
They lead to two problems: 1. The change to set TESTNUM before the test instead of after broke a few tests that relied on the old behavior. 2. Some tests in the v variant do something in the exception handler such that when they get an unaligned access exception, they end up stuck in a loop of unaligned access exceptions and the exception handler set up in the test is never called.
2022-06-06Test unaligned ld accesses.Tim Newsome1-0/+27
Identical to the lw change in #391.
2022-06-06Add unaligned test cases for lwTim Newsome1-0/+23
The test passes if either the target register contains the correct value, or the target raises a misaligned load exception.
2022-06-06Set TESTNUM before executing code.Tim Newsome1-1/+1
Tests that might cause a trap during their code need TESTNUM (gp) set so the trap handler can correctly identify which test is running, and also report that to the user in case the test fails.
2022-05-28Permit mtval to be zero in misaligned address test, fixes #389 (#390)Luke Wren1-0/+2
2022-03-08Add Zfh and Svnapot to Spike ISA stringAndrew Waterman1-2/+2
Otherwise, "make run" doesn't work.
2021-07-22Fix #352 (#353)Daniel Lustig1-2/+2
Thanks to @pdonahue-ventana for pointing this out
2021-07-21Move the Svnapot test to its own folder (#351)Daniel Lustig4-1/+10
...since not all implementations will support it
2021-07-19Add a test for Svnapot (#349)Daniel Lustig2-0/+173
2021-06-01Enable access to cycle counter before trying to write itAndrew Waterman1-0/+13
There are two reasons that writing the cycle counter might trap: - Because it's a read-only CSR - Because mcounteren.CY=0 or scounteren.CY=0 We want to make sure we're testing the first property, so set up the other bits accordingly.
2021-06-01Test all four ways of reading a read-only CSRAndrew Waterman1-0/+8
2021-05-12Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: ↵SLAMET RIANTO2-0/+2
(#337) Added "#define stvec mtvec" under __MACHINE_MODE ifdef. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-05-10Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support ↵SLAMET RIANTO3-0/+52
CLIC mode. (#336) illegal.S: - After the test enters supervisor mode, check if paging is supported. - If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following: -- SFENCE.VMA causing illegal instruction trap regardless of TVM. -- Access to SATP does not trap. -- Jump to the same TSR check as regular S-mode -- End test sbreak.S & scall.S: - Before checking for scause, check if the core is in CLIC-mode (mtvec[1]). - If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value. - Otherwise, don't mask off any scause bits as in the original test. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-02-01Align mtvec in rv32mi-p-shamt testAndrew Waterman1-0/+1
Resolves #323
2021-01-08Don't rely on the implementation-specific WFI time limit (#318)Paul Donahue1-18/+0
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset * Remove testcase that relies on the implementation-specific WFI time limit being 0.
2021-01-04Disable rv32ua/rv64ua LR/SC test case 4 (#316)Ben Marshall1-8/+14
- After discussion in riscv/riscv-tests#315, disable this test case, as it makes implementation assumptions which are not valid with respect to the specification. - Leave code present but commented out. On branch dev/benm-disable-lrsc-test-4 Changes to be committed: modified: isa/rv64ua/lrsc.S
2020-12-16Refactor rv64ud structural test to match format of other tests (#311)Kathlene Hurt1-11/+13
* Refactored rv64ud structural test to use pass/fail macros and test numbers * More clean up so test actually jumps to fail label
2020-12-08Add rd=x0 test case to csr test (#308)Takahiro1-0/+1
2020-12-07Fix minor typo (#307)Takahiro1-1/+1
2020-11-20Only attempt to build tests supported by compilerAndrew Waterman19-38/+6
Resolves #303
2020-11-11add zfh (float16) test case and related macros (#301)Chih-Min Chao26-0/+769
* ext: add zfh extension test case and related macro Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * build: add zfh to target Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-19use registers present on rv32e (#299)Sandeep Rajendran1-4/+4
2020-03-21Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5Andrew Waterman1-7/+7
2020-03-21Move self-modifying 'fence.i' ops to .data memory section (#269)WRansohoff1-6/+14
Co-authored-by: WRR <-@->
2020-03-19Fix comments error in fmin.S (#267)Mohanson2-4/+4
2020-03-18Have both rs=rd and rs!=rd cases in csr.S (#263)Takahiro1-12/+15
2020-03-18Fix shamt.S header (#264)Takahiro1-2/+2
2020-03-16Add a test case rs = rd to jalr.S (#258)Takahiro1-0/+16
2020-03-11Add comment explaining convoluted rv64mi-p-scall behaviorAndrew Waterman1-0/+6
2020-03-11Revert "scall: make the intention of the test in machine mode more clear (#246)"Andrew Waterman1-6/+1
This reverts commit 6fa1896b2a3f581359f0b6a952542f814e30602c. Resolves #256
2020-03-11Setup a multilevel page table to avoid misaligned superpages caused by ↵Cedric Orban1-0/+4
variable DRAM_BASE (#255) * setup a multilevel page table to avoid misaligned superpages * Revert "setup a multilevel page table to avoid misaligned superpages" This reverts commit 73c142df7dbdd3a5347ef228a368fb58b0b12be5. * statically fail if DRAM_BASE is not superpage-aligned
2020-03-06Don't assume reset state of mscratch (#254)Paul Donahue1-1/+1
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset
2020-03-02enable rv32e compatability by replacing reg x29 with reg x7 (#250)Cedric Orban1-12/+12
2020-02-21scall: make the intention of the test in machine mode more clear (#246)Nils Asmussen1-1/+6
2020-02-20Fix rv64mi-p-csr on systems with FPUsAndrew Waterman1-2/+3
3a98ec2e306938cce07ab15e3678d670611aa66d introduced a subtle bug because of the value of TESTNUM at the point an expected exception was taken. Fix by moving the new tests earlier in the program.
2020-01-31Added CSR test cases on whether writing 0 to CSR works, as that might get ↵Torbjørn Viem Ness1-0/+2
overlooked by implementors because some CSR operations should ignore writes if source is x0 (#236)
2019-11-04Remove cruft from icache-alias testAndrew Waterman1-35/+0
2019-11-04Add rv64si-p-icache-aliasAndrew Waterman2-0/+177
This test checks that an I$ appears to be physically indexed.
2019-07-29Support RV32E. Fixed #198 (#200)Leway Colin3-42/+42
2019-04-20masking no longer required.Neel1-16/+0
2019-04-20removing check for reset value of type in mcontrolNeel1-10/+8
2019-04-20fix for #159 #158Neel1-4/+7
2019-03-17Rename TEST_SRL to TEST_SRLI to avoid conflicts with another TEST_SRL (#183)Pavel I. Kryukov1-18/+18
2019-01-26Fix comments for shift amount. (#177)takeoverjp3-3/+3
2018-12-18Avoid using t3 and t4 for supporting RV32E (#173)zhonghochen1-5/+6
2018-11-16Test memory content on failing SC (#171)Florian Zaruba1-4/+10
2018-09-08RV64 s{ll,ra,rl}w tests with non-canonical valuesTommy Thorn6-0/+42
2018-09-06Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) ↵Andrew Waterman1-1/+1
(#159)" This reverts commit 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028, under the advisement of @tommythorn in #158.
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