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issue#577
In the newest riscv spec(2021 or later), two csr register
"sptbr"(0x180) "s/mbadaddr"(0x243) were removed,
and upgraded to "satp" "s/mtval". Together with more functions.
This commit rename them to pass compile.
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Continuation of fee361fd89edd4ac031a570affde16f4f84414e9
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By using Zca-friendly registers, we can reuse the existing tests to get
quick-and-dirty coverage of Zca, when the assembler is told to use Zca.
(This doesn't break non-Zca targets.)
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See https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214
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Signed-off-by: Roger Chang <rogerycchang@google.com>
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Signed-off-by: Roger Chang <rogerycchang@google.com>
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Signed-off-by: Roger Chang <rogerycchang@google.com>
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Signed-off-by: Roger Chang <rogerycchang@google.com>
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If Svnapot is not implemented, a page fault will occur when accessing a page with napot specified.
In this case, let the test pass.
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Include Zicntr in Spike ISA string
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Add more tests for amo[max/maxu/min/minu]_w
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Spike no longer enables Zicntr by default, so turn it on explicitly.
cc @jerryz123
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The trap handler for norvc systems has an incorrect jump offset
Signed-off-by: Yujia Qiao <code@rapiz.me>
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...because the ma_data test requires this feature.
Don't merge until https://github.com/riscv-software-src/riscv-isa-sim/pull/1206 is merged.
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It is allowed that M-mode only implementation could skip cycle/instret
if the Zicntr is not included.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Assume that misaligned loads work correctly.
Passes `make -C isa run` against spike (both with and without misaligned
support).
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Cover lh, lw, and ld (only on rv64).
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Tests that might cause a trap during their code need TESTNUM (gp) set so
the trap handler can correctly identify which test is running, and also
report that to the user in case the test fails.
Fix up shamt.S and csr.S to handle the new behavior.
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They lead to two problems:
1. The change to set TESTNUM before the test instead of after broke a
few tests that relied on the old behavior.
2. Some tests in the v variant do something in the exception handler
such that when they get an unaligned access exception, they end up
stuck in a loop of unaligned access exceptions and the exception
handler set up in the test is never called.
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Identical to the lw change in #391.
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The test passes if either the target register contains the correct
value, or the target raises a misaligned load exception.
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Tests that might cause a trap during their code need TESTNUM (gp) set so
the trap handler can correctly identify which test is running, and also
report that to the user in case the test fails.
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Otherwise, "make run" doesn't work.
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Thanks to @pdonahue-ventana for pointing this out
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...since not all implementations will support it
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There are two reasons that writing the cycle counter might trap:
- Because it's a read-only CSR
- Because mcounteren.CY=0 or scounteren.CY=0
We want to make sure we're testing the first property, so set up
the other bits accordingly.
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(#337)
Added "#define stvec mtvec" under __MACHINE_MODE ifdef.
Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
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CLIC mode. (#336)
illegal.S:
- After the test enters supervisor mode, check if paging is supported.
- If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following:
-- SFENCE.VMA causing illegal instruction trap regardless of TVM.
-- Access to SATP does not trap.
-- Jump to the same TSR check as regular S-mode
-- End test
sbreak.S & scall.S:
- Before checking for scause, check if the core is in CLIC-mode (mtvec[1]).
- If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value.
- Otherwise, don't mask off any scause bits as in the original test.
Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
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Resolves #323
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* Bump riscv-test-env
* Merge master
* Don't assume that mscratch is initialized to a particular value on reset
* Remove testcase that relies on the implementation-specific WFI time limit being 0.
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- After discussion in riscv/riscv-tests#315, disable this test case, as it
makes implementation assumptions which are not valid with respect to the
specification.
- Leave code present but commented out.
On branch dev/benm-disable-lrsc-test-4
Changes to be committed:
modified: isa/rv64ua/lrsc.S
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* Refactored rv64ud structural test to use pass/fail macros and test numbers
* More clean up so test actually jumps to fail label
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Resolves #303
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* ext: add zfh extension test case and related macro
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
* build: add zfh to target
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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