| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2018-04-30 | [rv64ua/lrsc] Initialize memory read out. (#135) | Christopher Celio | 1 | -1/+3 | |
| * [rv64ua/lrsc] Initialize memory read out. Even though the load contents are discarded, this un-initialized memory value can lead to a divergence for co-simulation between two different RISC-V designs. * [rv64ua/lrsc] Use .skip instead of .align. | |||||
| 2018-04-09 | Fix #120: Instructions 'sll' are replaced with 'slli' in rv64ui/slli.S (#121) | Andrei Tatarnikov | 1 | -3/+3 | |
| 2018-03-21 | Make misa.C test conform to Hauser proposal | Andrew Waterman | 1 | -43/+10 | |
| See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7 | |||||
| 2018-02-27 | Add test for clearing misa.C while PC is misaligned (#117) | Andrew Waterman | 1 | -1/+79 | |
| See https://github.com/riscv/riscv-isa-manual/pull/139 | |||||
| 2018-01-02 | Test access exception behavior for illegal addresses (#111) | Andrew Waterman | 2 | -0/+71 | |
| OK'd by @palmer-dabbelt | |||||
| 2017-11-27 | Rename sbadaddr to satp | Andrew Waterman | 2 | -3/+3 | |
| 2017-11-26 | Rv32ud tests (#108) | Torbjørn | 23 | -0/+318 | |
| * Probably implemented the changes required to support fadd test for rv32ud * Created test files in rv32ud, implemented working(?) test for ldst * fclass, fcvt_w, fmin and recoding seem to be working now * Got fdiv (and sqrt) tests working * fmadd tests seem to work * fcmp works * [WIP] fcvt working, but lacks a 32-bit implementation of the final test * Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST * Added Makefrag for rv32ud tests and included in main isa Makefile * Don't run 64-bit tests if the defined XLEN is 32 | |||||
| 2017-11-22 | Check sepc for rv64si/scall test. (#107) | Christopher Celio | 1 | -0/+4 | |
| Closes #105. | |||||
| 2017-11-20 | Check mtval in rv64mi-p-illegal (#104) | Andrew Waterman | 1 | -0/+11 | |
| Closes #103 | |||||
| 2017-11-11 | Make sure that code is 4-byte aligned before disabling rvc (#100) | Andrew Waterman | 4 | -1/+5 | |
| 2017-11-09 | Make rv64mi-p-ecall work when U-mode is not present | Andrew Waterman | 1 | -1/+17 | |
| 2017-11-09 | Use mstatus.MPP to check existence of U-mode | Andrew Waterman | 1 | -5/+6 | |
| misa is allowed to be hardwired to 0, so checking its U bit could incorrectly suggest that U-mode is not supported. | |||||
| 2017-11-01 | SBREAK test now checks EPC value. (#92) | Christopher Celio | 1 | -0/+4 | |
| Closes #89 | |||||
| 2017-10-30 | Remove cache miss test from last AMO test. (#88) | Richard Xia | 1 | -17/+0 | |
| Follow-up to b68b39031a730ecc155ed87fba2ed5f111d0ab07. The 64KiB allocated by the code to force a cache miss makes it impossible to run the test from any memories that are smaller 64KiB, such as scratchpad memories or LIMs. Since this is trying to test microarchitectural behavior, they don't belong in these ISA tests anyway. | |||||
| 2017-10-30 | Declare trap handlers as global symbols. (#87) | Richard Xia | 8 | -0/+9 | |
| This allows them to be referenced by other files, such as a test environment that lives in a separate compilation unit. | |||||
| 2017-10-26 | Verify that mtval/stval is written correctly on misaligned fetch | Andrew Waterman | 1 | -1/+9 | |
| 2017-10-26 | Fix rv64mi-csr for the case where U-mode is not available. (#86) | Richard Xia | 1 | -0/+16 | |
| 2017-09-01 | Improve ma_fetch test to cover JAL and branches | Andrew Waterman | 1 | -1/+48 | |
| 2017-08-07 | rv64[ms]i-csr: Only emit F instructions when compiled for F. | Richard Xia | 1 | -1/+6 | |
| 2017-08-04 | RV32 div tests should use -2^31 for min value, not -2^63 | Andrew Waterman | 3 | -9/+9 | |
| 2017-08-04 | Improve RVC test | Andrew Waterman | 1 | -3/+2 | |
| Make the page-crossing instruction non-idempotent to detect erroneously executing the first 16 bits of the instruction with garbage MSBs. | |||||
| 2017-05-22 | minNum -> minimumNumber | Andrew Waterman | 2 | -4/+16 | |
| 2017-05-17 | Manually assemble bad shift amount, since assembler rejects | Andrew Waterman | 1 | -1/+1 | |
| Resolves #51 | |||||
| 2017-05-05 | Check UXL in sstatus | Andrew Waterman | 1 | -0/+5 | |
| 2017-05-05 | Test that superpage PTEs trap when PPN LSBs are set | Andrew Waterman | 1 | -0/+18 | |
| 2017-05-05 | Regularize control flow in dirty-bit test | Andrew Waterman | 1 | -8/+12 | |
| 2017-04-14 | Fix illegal-instruction test when S-mode is not implemented | Andrew Waterman | 1 | -10/+14 | |
| 2017-04-10 | Improve fp ldst/move tests; remove redundant fsgnj tests | Andrew Waterman | 9 | -122/+126 | |
| 2017-04-07 | Retrofit rv64mi-p-illegal to test vectored interrupts | Andrew Waterman | 1 | -7/+41 | |
| 2017-04-07 | Remove defunct IPI tests | Andrew Waterman | 4 | -62/+0 | |
| 2017-04-05 | Make ma_addr test work for systems with misaligned ld/st | Andrew Waterman | 1 | -34/+66 | |
| 2017-03-30 | Expand dirty-bit test to test MPRV and SUM | Andrew Waterman | 1 | -27/+30 | |
| 2017-03-27 | Separate page faults from physical memory access exceptions | Andrew Waterman | 1 | -1/+1 | |
| 2017-03-22 | Clean up benchmarks build | Andrew Waterman | 1 | -2/+0 | |
| 2017-03-21 | Allow supervisor access to user pages in dirty-bit test | Andrew Waterman | 1 | -1/+1 | |
| 2017-03-21 | Avoid x3 (gp), which is now TESTNUM | Andrew Waterman | 14 | -106/+106 | |
| 2017-03-13 | Test mstatus.TW, mstatus.TVM, and mstatus.TSR features | Andrew Waterman | 1 | -1/+105 | |
| 2017-03-09 | Don't link ISA tests against libc | Andrew Waterman | 1 | -1/+1 | |
| 2017-03-09 | Permit flexible dirty-bit behavior | Andrew Waterman | 2 | -18/+28 | |
| 2017-03-09 | Check mbadaddr in ma_addr test | Andrew Waterman | 1 | -0/+4 | |
| 2017-02-01 | Use NaN macros | Andrew Waterman | 4 | -8/+8 | |
| 2017-02-01 | Test FMIN/FMAX NaN behavior | Andrew Waterman | 3 | -0/+15 | |
| See https://github.com/riscv/riscv-isa-sim/issues/76 | |||||
| 2017-01-31 | Test qNaN and sNaN inputs to FP comparisons | Andrew Waterman | 3 | -18/+44 | |
| 2017-01-04 | Specify Spike ISA explicitly | Andrew Waterman | 1 | -2/+2 | |
| 2017-01-04 | Remove Hwacha macros | Andrew Waterman | 2 | -645/+0 | |
| 2017-01-04 | Mask off large constants for RV32 | Andrew Waterman | 1 | -23/+25 | |
| 2016-12-12 | Pass newly updated -march, -mabi options to gcc | Andrew Waterman | 1 | -15/+15 | |
| 2016-12-06 | avoid non-standard predefined macros | Andrew Waterman | 10 | -20/+20 | |
| 2016-11-21 | Remove cache miss test from all but one AMO test | Andrew Waterman | 17 | -161/+2 | |
| This doesn't reduce coverage for cache-based RV64 systems, but will improve test runtime and work around the need for smaller test footprint for scratchpad-based RV32 systems. I would argue that these microarchitectural tests should be in the domain of torture, and that the last one should be removed, too. | |||||
| 2016-11-01 | Make sure FP stores don't write memory if mstatus.FS=0. | Andrew Waterman | 1 | -8/+22 | |
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index : riscv-tests.git | |
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