index
:
riscv-tests.git
attempt-travis-fix
ceasetest2
compliance_tests
cs152-sp18-lab3
debug
debug-0.13
debug-clear-satp
debug-delete-sim
debug_auth
debug_disassemble
disable_unavailable
dma-memcpy
eos20-bringup
hw_watchpoint
interrupts
master
misc
no_progbuf
priv
privchange-dontdeleteme
python3
rekall
resume_from_trigger
riscv-tests-sail
rtos
rvt-master
smi-demo
split-isa-tests
sqrt-171
tmp
trap_entry_align
trap_entry_align-1
travis-dev
trigger_priority
usb_error
xlen_fix
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
isa
/
rv64si
Age
Commit message (
Expand
)
Author
Files
Lines
2022-06-07
Set TESTNUM before executing code.
Tim Newsome
1
-3
/
+2
2021-07-21
Move the Svnapot test to its own folder (#351)
Daniel Lustig
2
-173
/
+0
2021-07-19
Add a test for Svnapot (#349)
Daniel Lustig
2
-0
/
+173
2021-06-01
Enable access to cycle counter before trying to write it
Andrew Waterman
1
-0
/
+13
2021-06-01
Test all four ways of reading a read-only CSR
Andrew Waterman
1
-0
/
+8
2021-05-12
Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: (#...
SLAMET RIANTO
2
-0
/
+2
2021-05-10
Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support C...
SLAMET RIANTO
2
-0
/
+14
2020-12-08
Add rd=x0 test case to csr test (#308)
Takahiro
1
-0
/
+1
2020-11-20
Only attempt to build tests supported by compiler
Andrew Waterman
1
-2
/
+0
2020-03-21
Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5
Andrew Waterman
1
-7
/
+7
2020-03-18
Have both rs=rd and rs!=rd cases in csr.S (#263)
Takahiro
1
-12
/
+15
2020-03-11
Add comment explaining convoluted rv64mi-p-scall behavior
Andrew Waterman
1
-0
/
+6
2020-03-11
Revert "scall: make the intention of the test in machine mode more clear (#246)"
Andrew Waterman
1
-6
/
+1
2020-03-11
Setup a multilevel page table to avoid misaligned superpages caused by variab...
Cedric Orban
1
-0
/
+4
2020-03-06
Don't assume reset state of mscratch (#254)
Paul Donahue
1
-1
/
+1
2020-02-21
scall: make the intention of the test in machine mode more clear (#246)
Nils Asmussen
1
-1
/
+6
2020-02-20
Fix rv64mi-p-csr on systems with FPUs
Andrew Waterman
1
-2
/
+3
2020-01-31
Added CSR test cases on whether writing 0 to CSR works, as that might get ove...
Torbjørn Viem Ness
1
-0
/
+2
2019-11-04
Remove cruft from icache-alias test
Andrew Waterman
1
-35
/
+0
2019-11-04
Add rv64si-p-icache-alias
Andrew Waterman
2
-0
/
+177
2018-08-21
Changing the register mstatus is read into (#152)
Srivatsa Yogendra
1
-2
/
+2
2018-08-20
Revert "Fix to solve the failing tests shamt, csr and scall (#151)"
Andrew Waterman
2
-52
/
+5
2018-08-17
Fix to solve the failing tests shamt, csr and scall (#151)
Srivatsa Yogendra
2
-5
/
+52
2018-03-21
Make misa.C test conform to Hauser proposal
Andrew Waterman
1
-43
/
+10
2018-02-27
Add test for clearing misa.C while PC is misaligned (#117)
Andrew Waterman
1
-1
/
+79
2017-11-27
Rename sbadaddr to satp
Andrew Waterman
1
-1
/
+1
2017-11-22
Check sepc for rv64si/scall test. (#107)
Christopher Celio
1
-0
/
+4
2017-11-11
Make sure that code is 4-byte aligned before disabling rvc (#100)
Andrew Waterman
1
-0
/
+1
2017-11-09
Make rv64mi-p-ecall work when U-mode is not present
Andrew Waterman
1
-1
/
+17
2017-11-09
Use mstatus.MPP to check existence of U-mode
Andrew Waterman
1
-5
/
+6
2017-11-01
SBREAK test now checks EPC value. (#92)
Christopher Celio
1
-0
/
+4
2017-10-30
Declare trap handlers as global symbols. (#87)
Richard Xia
5
-0
/
+5
2017-10-26
Verify that mtval/stval is written correctly on misaligned fetch
Andrew Waterman
1
-1
/
+9
2017-10-26
Fix rv64mi-csr for the case where U-mode is not available. (#86)
Richard Xia
1
-0
/
+16
2017-09-01
Improve ma_fetch test to cover JAL and branches
Andrew Waterman
1
-1
/
+48
2017-08-07
rv64[ms]i-csr: Only emit F instructions when compiled for F.
Richard Xia
1
-1
/
+6
2017-05-05
Check UXL in sstatus
Andrew Waterman
1
-0
/
+5
2017-05-05
Test that superpage PTEs trap when PPN LSBs are set
Andrew Waterman
1
-0
/
+18
2017-05-05
Regularize control flow in dirty-bit test
Andrew Waterman
1
-8
/
+12
2017-03-30
Expand dirty-bit test to test MPRV and SUM
Andrew Waterman
1
-27
/
+30
2017-03-27
Separate page faults from physical memory access exceptions
Andrew Waterman
1
-1
/
+1
2017-03-21
Allow supervisor access to user pages in dirty-bit test
Andrew Waterman
1
-1
/
+1
2017-03-09
Permit flexible dirty-bit behavior
Andrew Waterman
1
-16
/
+26
2016-11-01
Make sure FP stores don't write memory if mstatus.FS=0.
Andrew Waterman
1
-8
/
+22
2016-08-26
Update to new breakpoint & counter spec
Andrew Waterman
1
-6
/
+6
2016-07-22
skip user-mode trap tests in rv32mi/rv64mi-p-csr if no user mode
Howard Mao
1
-0
/
+9
2016-07-22
Move dirty bit test to rv64si directory
Andrew Waterman
2
-0
/
+94
2016-07-22
Make ma_fetch test robust against code size changes
Andrew Waterman
1
-2
/
+4
2016-07-11
Remove instruction width assumptions to support RVC
Andrew Waterman
4
-6
/
+6
2016-07-07
Update WFI test for priv v1.9
Andrew Waterman
1
-2
/
+3
[next]