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2023-07-17debug: Create UnavailableCycleTestTim Newsome1-0/+27
Use new spike mechanism to test OpenOCD behavior when a hart becomes unavailable, and then available again.
2023-07-17debug: CeaseRunTest -> UnavailableRunTestTim Newsome2-3/+23
Use new spike mechanism to test OpenOCD behavior when the current hart becomes unavailable while running. Create ThreadTerminated exception.
2023-07-17debug: CeaseMultiTest -> UnavailableMultiTestTim Newsome2-8/+30
Use the new spike mechanism to test OpenOCD behavior when a hart becomes unavailable while running. Create CommandException.
2023-07-17Interact with OpenOCD CLI over stdin/stdout.Tim Newsome1-39/+102
It's a bit messy to read the log file to get the output, but it seems to be flushed often so that this works. Also, added the `targets` method for retrieving the list of targets, and `wait_until_running` method to wait until all targets are in a running state.
2023-07-17debug: Add support_unavailable_control property.Tim Newsome8-0/+10
2023-07-17parkOtherHarts() already defaults to ceaseTim Newsome1-1/+1
2023-07-17Move "monitor targets" calls into a central place.Tim Newsome2-3/+1
2023-07-17Move `import random`Tim Newsome1-1/+2
Just so it's easier to quickly comment out code and hard-code the target to use without pylint complaining. This really should be a command line option.
2023-07-14Remove old warning check in RepeatReadTestEvgeniy Naydanov1-4/+0
2023-07-13Merge pull request #490 from riscv-software-src/flushregsTim Newsome1-4/+4
debug: flushregs -> maintenance flush register-cache
2023-07-13debug: flushregs -> maintenance flush register-cacheTim Newsome1-4/+4
flushregs is deprecated.
2023-07-13Add an exclude list for known failing Hifive1 tests (#485)Marek Vrbka1-0/+28
* Add an exclude list for known failing Hifive1 tests This commit adds a list of known failing tests based on: https://github.com/riscv/riscv-openocd/issues/869#issue-1769176709 * Fix name of the HiFive1 flash target Signed-off-by: Marek Vrbka <133884222+MarekVCodasip@users.noreply.github.com> --------- Signed-off-by: Marek Vrbka <133884222+MarekVCodasip@users.noreply.github.com>
2023-07-10Merge pull request #486 from en-sc/en-sc/warning-repeat-readTim Newsome1-2/+15
change warning check in RepeatReadTest
2023-07-07Merge pull request #487 from riscv-software-src/debug_pathTim Newsome2-8/+4
debug: Don't rely on RISCV env
2023-07-07change warning check in RepeatReadTestEvgeniy Naydanov1-2/+15
2023-07-05Merge pull request #484 from TommyMurphyTM1234/masterTim Newsome1-2/+2
Fix for test program compilation failures due to lack of `zicsr` extension in `-march=rvXX...`
2023-06-30debug: Don't rely on RISCV envTim Newsome2-8/+4
That made sense when mostly people used riscv-tools, but now they get tools from all sorts of places and most of them are suitable for the debug tests. Also document RISCV_TESTS_DEBUG_GCC and RISCV_TESTS_DEBUG_GDB environment variables in the README. The github workflows that rely on these tests don't use the Makefile, but instead invoke gdbserver.py directly, so they're not affected by this change. Fixes #481
2023-06-30Fix for https://github.com/riscv-software-src/riscv-tests/issues/482Tommy Murphy1-2/+2
2023-06-29debug: pylint fix.Tim Newsome1-2/+2
2023-06-29Merge pull request #480 from riscv-software-src/pylintTim Newsome1-4/+7
Github workflow to run pylint against debug tests
2023-06-29Add --target-timeout to debug test script.Tim Newsome1-1/+7
I'm using this to greatly reduce the timeout when I'm reproducing a failure I know is going to time out.
2023-06-29Merge pull request #478 from Du-Chao/masterTim Newsome1-4/+16
debug: optimize the FreeRtosTest case.
2023-06-27Pylint fixes.Tim Newsome1-4/+7
2023-06-27Merge pull request #477 from MarekVCodasip/test-exclusionTim Newsome4-1/+52
Add a way to exclude tests by specifying an exclusion file
2023-06-27Add a way to exclude tests by specifying an exclusion fileMarek Vrbka4-1/+52
This patch adds a way to specify a yaml file which specifies either for each target individually or for all targets to exclude tests. Example file format is included in excluded.yaml.example.
2023-06-15debug: optimize the FreeRtosTest case.Chao Du1-4/+16
To make sure the rtos module of OpenOCD works well. Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-06-12Get gcc and gdb path from environment.Tim Newsome1-7/+10
If the environment variables aren't set, then use the same defaults as previously. My current set of tools use riscv64-elf-gcc and riscv64-elf-gdb, and this makes it trivial to use them.
2023-05-25debug: New pylint => new warnings => new cleanupsTim Newsome4-24/+34
- Replace general "Exception" with "GdbServerError" in gdbserver.py for when no samples are collected - Replace general "Exception" with "TargetsException" in targets.py for XLEN mismatch - Introduce "TestLibError" exception in testlib.py and replace general exceptions in various locations - Update pylint.rc to remove overgeneral-exceptions warning
2023-05-10New pylint, so make everything clean again.Tim Newsome2-61/+8
2023-05-01Update OpenOCD cfg files to new syntaxTim Newsome7-34/+34
We were using a variety of deprecated commands. The driving force behind this was the new way to use `expr{}` as the old way no longer works with mainline OpenOCD.
2023-03-01Fix intermittent IcountTest failure on multi hart.Tim Newsome1-1/+1
Don't build with -DMULTICORE because this is not a test that really does multicore. It's one where we just want to park the other harts.
2023-02-28Merge pull request #458 from Du-Chao/masterTim Newsome1-2/+2
debug: fix pylint error W0621 redefined-outer-name
2023-02-21debug: fix pylint error W0621 redefined-outer-nameChao Du1-2/+2
2023-02-16Add test for icount triggers.Tim Newsome1-0/+27
2023-02-02Fix EtriggerTest on multi-hart targets.Tim Newsome1-0/+1
Need to set the etrigger on the hart we're running the test against.
2023-01-06debug: Add Itrigger test.Tim Newsome1-0/+26
2023-01-06debug: Tweak interrupt.c, so a test can run to exit()Tim Newsome1-1/+4
2022-12-29debug: Add etrigger test.Tim Newsome2-1/+20
2022-12-14debug: Add CeaseRunTestTim Newsome1-0/+23
Test that we work correctly when the hart we're debugging ceases to respond while it's running.
2022-12-14debug: Add CeaseStepiTest.Tim Newsome2-3/+37
Test that we work correctly when the hart we're debugging ceases to respond during stepi. Add wait parameter to Gdb.stepi(), in case stepi isn't expected to complete. Parse "could not read registers" error from gdb
2022-12-14debug: Create CeaseMultiTest. (#436)Tim Newsome2-2/+55
Confirm basic debug still works when other harts have been parked using a `cease` instruction. Check that the unavailable harts are inaccessible from gdb. Add Gdb.expect() Parse "unknown thread" error from gdb.
2022-12-14debug: Remove unnecessary exit() functions. (#437)Tim Newsome3-11/+4
Also make the semi-hosting test program return 10. That's more fragile than returning 0, so makes for a better test.
2022-12-08Fix regression in VcsSim introduced by #334 (#440)Jerry Zhao1-0/+1
2022-12-01debug: Disassemble memory when a failure happens. (#432)Tim Newsome1-1/+1
This gives you less noise in the log, and more chance of figuring out what code was actually executed.
2022-12-01`flush regs` -> `maintenance flush register-cache` (#431)Tim Newsome1-1/+1
`flush regs` is being deprecated.
2022-12-01debug: Park unused harts with a cease instruction. (#434)Tim Newsome3-2/+23
`cease` is not a standard RISC-V extension, but is (was?) implemented in Rocket, and also exists in some SiFive cores. It's useful to test OpenOCD behavior when a hart becomes unavailable. See also https://github.com/chipsalliance/rocket-chip/issues/1868
2022-12-01Share exit() among more tests. (#433)Tim Newsome3-16/+9
2022-11-10SvNNTest needs 32KB of RAM. (#428)Tim Newsome2-4/+7
Also change the test itself to require less RAM than it did previously. (It had required more than 32KB.)
2022-11-04Make MulticoreRegTest work with real hardware.Tim Newsome2-17/+19
It would fail intermittently. We can't guarantee all harts resume simultaneously. When we let multiple harts run to a breakpoint at the end of the same loop, one is likely to get there first, and the second won't make it. To avoid this problem, run for a short amount of time instead of to a breakpoint.
2022-11-03Fix PrivChange test address comparison. (#427)Tim Newsome1-3/+4
Before it might fail incorrectly, because main was close to trap_entry.
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