aboutsummaryrefslogtreecommitdiff
path: root/debug
AgeCommit message (Collapse)AuthorFilesLines
2022-05-16V implies FD now. (#382)Tim Newsome1-3/+3
Adjust test to work with that.
2022-04-25Add EbreakTest. (#380)Tim Newsome2-0/+62
* Add EbreakTest. Confirm correct behavior when somebody bakes an ebreak instruction into their code. * Forgot to commit ebreak.c
2022-04-07Make download test data const. (#378)Tim Newsome1-2/+2
That way it can go into flash.
2022-03-03With new OpenOCD, gdb prints thread info differently (#373)Tim Newsome1-1/+2
It includes the name in quotes: ```* 2 Thread 1 "Current Execution" (Name: Current Execution) 0x10000100 in main``` Just ignore that part.
2022-03-03Add assert to MemorySampleTest. (#370)Tim Newsome1-0/+1
Now it will give slightly more helpful output if it fails.
2022-02-09Debug test to check that stepping doesn't inappropriately switch to Thread 1 ↵Greg Savin1-0/+21
(#369)
2022-01-06Add gdb.interact() for debug tests. (#367)Tim Newsome1-0/+18
This feature lets you easily interact with the gdb after the test has run to a certain point.
2021-11-29Fix TranslateTests. (#365)Tim Newsome2-5/+7
They used to set U, A, D, in intermediate page table entries which is no longer allowed.
2021-11-12Set `riscv resume_order reversed`. (#363)Tim Newsome1-0/+2
The tests don't confirm that the order actually changes, but at least the code that does the work now is executed during the tests.
2021-11-12Create DisconnectTest. (#364)Tim Newsome2-32/+53
Disconnects from gdb, and then reconnects, making sure that didn't change any of the registers. This test will start passing when https://github.com/riscv/riscv-openocd/pull/661 merges.
2021-11-12Add timing output to DebugTurboStep. (#362)Tim Newsome1-1/+5
Useful for estimating interactive performance.
2021-10-05Remove slen. (#360)Tim Newsome4-22/+16
It's not an argument to spike anymore. Also switch testing the vector unit from multi-gdb to `-rtos hwthread`. This exposes a bug in OpenOCD (which is already fixed).
2021-07-19Debug tests: catch write to nonexistent trigger registers in entry.S (#348)Luke Wren1-0/+7
2021-06-08Tweaks for multispike. (#339)Tim Newsome3-9/+19
1. Don't run all tests in multi-spike. Extra coverage is negligible, and it just takes too long. 2. Increase a few timeouts.
2021-05-20Test multiple heterogeneous spike instances. (#338)Tim Newsome6-63/+70
2021-05-07Test daisy chained homogeneous spike instances. (#334)Tim Newsome9-40/+303
* Test debugging multiple spikes in a daisy chain. * Hugely speed up rbb_daisychain. Now 2 dual-hart spikes are less than 4x slower than a single dual-hart spike. * WIP * Test daisy chained homogeneous spike instances. For OpenOCD, this means we're checking that we can talk to multiple TAPs. Next up is heterogeneous testing. * Enable Sv48Test. Didn't mean to disable it with this commit. * Test authentication again. Another change I hadn't meant to push...
2021-04-13Add FreeRTOS smoke tests. (#333)Tim Newsome9-15/+103
* Add FreeRTOS smoke tests. Make sure that OpenOCD can access all threads in a FreeRTOS binary on single-hart RV32 and RV64. * Also test `-rtos FreeRTOS`.
2021-02-11Add early_applicable() to a few tests. (#325)Tim Newsome1-7/+8
It's faster to figure out there that the test is going to N/A.
2021-01-25Smoketest that vl and vtype can be modified. (#320)Tim Newsome2-29/+12
2021-01-08Disable V extension when compiler doesn't support it. (#317)Tim Newsome1-2/+24
This allows the vast majority of these tests to work with compilers that don't support the V extension yet, which is helpful for people who aren't using a vector branch of the compiler. Specifically, this will hopefully allow us to run regression tests against OpenOCD on every change, per https://github.com/riscv/riscv-openocd/pull/563.
2021-01-07Park other harts in TranslateTest. (#313)Tim Newsome1-0/+1
This fixes an intermitten failure when running these tests.
2021-01-07Stop testing `-rtos riscv`. (#314)Tim Newsome2-23/+3
As of tomorrow that feature is officially no longer supported in OpenOCD, so stop testing it.
2020-12-31Make HiFiveUnleashed tests clean.Tim Newsome7-1/+14
HiFiveUnleashed-flash fails som address translation tests. Possibly that would be fixed when https://github.com/riscv/riscv-tests/pull/313 merges.
2020-12-18Add test for new OpenOCD `riscv info` command. (#310)Tim Newsome1-0/+13
2020-12-18Revive and expand invalid read test. (#309)Tim Newsome1-12/+19
This test would have found https://github.com/riscv/riscv-openocd/issues/559.
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome10-1/+104
2020-10-08Expose registers on all harts in openocd cfgs (#297)Samuel Obuch2-4/+10
2020-08-31Add test for `riscv repeat_read`. (#293)Tim Newsome1-0/+34
2020-08-12Point people at a compiler that supports vectors. (#290)Tim Newsome1-1/+2
Addresses #289.
2020-08-06Add enable_rtos_riscv (#288)Tim Newsome1-0/+2
This is now required to use `-rtos riscv`. Addresses the aside mentioned in #287.
2020-07-01Make pylint happy. (#285)Tim Newsome1-0/+1
2020-06-25Add manual hwbp test. (#283)Tim Newsome4-0/+98
Make sure OpenOCD cooperates when a user sets a trigger by writing tselect/tdata* directly.
2020-06-25Create a more sophisticated vector test (#284)Tim Newsome4-10/+248
* WIP * WIP * Vector test seems to work well with spike. * Check a0 in case the program didn't work right. * Return not applicable if compile doesn't support V
2020-05-26Test semihosting calls (#280)Tim Newsome9-5/+205
* Add a basic semihosting test. * Need to configure semihosting on each target. * WIP * Parse "cannot insert breakpoint" message. Also use sys.exit instead of exit, per new pylint's suggestion.
2020-05-18Parse "cannot insert breakpoint" message. (#279)Tim Newsome1-1/+8
Also use sys.exit instead of exit, per new pylint's suggestion.
2020-04-10Make TooManyHwbp more thorough. (#272)Tim Newsome1-1/+6
Test the behavior described in https://github.com/riscv/riscv-openocd/issues/76.
2020-04-10Change slen to a value that spike supports. (#271)Tim Newsome1-1/+3
2020-03-26Improve address translation tests (#261)Tim Newsome3-18/+54
* Improve address translation tests. Check that the mode we're testing is supported by hardware before running the test. Test with high address bits set, which catches a bug in OpenOCD. * Turn off PMP for address translation test. Otherwise it doesn't pass on HiFive Unleashed. * Run TranslateTest on random hart. Once https://github.com/riscv/riscv-openocd/pull/459 merges that will work.
2020-03-26Write a NOP program in PrivRw test. (#260)Tim Newsome2-9/+8
Otherwise it only passes intermittently when I change _start, which is very confusing.
2020-03-18Spike changed --varch syntax (#257)Tim Newsome1-2/+2
This was changed by https://github.com/riscv/riscv-isa-sim/pull/417
2020-03-18Specify misa for HiFive Unleashed. (#259)Tim Newsome1-0/+2
This saves a few seconds every time I run any test.
2020-03-05Clean up gdb parsing code. (#247)Tim Newsome1-42/+32
Also fix bug in parsing nan.
2020-03-05Add a simple mechanism to skip tests on targets. (#251)Tim Newsome2-1/+9
2020-02-14Add tests for vector register access (#244)Tim Newsome5-34/+137
* WIP * Add vector register smoketest. Also redo the gdb value parsing code to accommodate the more complicated way that vector registers look. * Test vector access a little more thoroughly. * Revert unnecessary changes.
2020-02-11Generate very different values on different harts. (#238)Tim Newsome2-4/+5
This way if you end up reading a value that you suspect might be coming from another hart/register, you can clearly see where it came from.
2020-02-11Run OpenOCD output through spike-dasm. (#239)Tim Newsome1-3/+9
If it's in the path, at least. This way you get human readable assembly in the log instead of hex values.
2020-02-11Look for \bmain\b instead of ' main '. (#237)Tim Newsome1-2/+2
2020-01-15Force DMI busy in all tests. (#235)Tim Newsome2-15/+44
This catches more corner cases where this may be a problem.
2020-01-09Smoke test virtual address translation support. (#233)Tim Newsome6-13/+231
* WIP * Smoke test virtual address support. Tests sv32, sv39, and sv48. Only explicitly tests 4K pages, but uses as large as possible pages to 1:1 map the rest of RAM so those sizes do get minimal coverage as well.
2019-12-18Hardcode misa values for all spike targets. (#227)Tim Newsome9-7/+27
`make` now takes 31s, `make all` takes 1m53s. The new CheckMisa test ensures that the misa value specified in the configuration is correct.
generated by cgit v1.1 at 2025-09-18 14:58:42 +0000