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2017-07-20Add back code to clean up triggers in entry.STim Newsome3-0/+24
Then for targets that can't handle this because they don't implement hmode, add a target setting that allows that to be specified.
2017-07-18Check all PCs after reset.Tim Newsome1-1/+7
2017-07-12Print out logs in more failure cases.Tim Newsome1-4/+10
2017-07-06debug: Make the 'out of reset' tests actually apply resetmwachs51-0/+5
2017-07-03Add gdb_setup to target for arbitrary gdb commandsTim Newsome2-0/+7
I'm using this for a target where misa is at an old address, to set riscv use_compressed_breakpoints off
2017-07-03Don't clear triggers during execution.Tim Newsome1-9/+0
This shouldn't affect triggers set by the debugger, because running code can't change those. When it does affect them, it breaks Hwbp1 which sets the breakpoint before running the program.
2017-06-27Tolerate missing misa register.Tim Newsome1-1/+7
At least in the test programs. There are other places where this causes trouble as well.
2017-06-26Move target definition into individual files.Tim Newsome26-284/+184
Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.
2017-06-22Add basic multicore test.Tim Newsome3-42/+128
2017-06-20Smoketest multicore.Tim Newsome3-14/+55
When connecting to gdb, select a random thread and use that for the current test. Also replace infinite_loop with something that will later allow smoketesting of more than one thread.
2017-06-19Write OpenOCD log when it crashes early.Tim Newsome1-2/+4
2017-06-16Store logs for all tests in logs/Tim Newsome1-30/+58
This creates a record of passing as well as failing tests, and gets rid of the log clutter that you previously ended up with in the current directory.
2017-06-15Test 64-bit addressing.Tim Newsome8-29/+90
The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000. Also a minor change to log file naming so that 'make all' works again. I'll fix this better later.
2017-06-09Add final echo to E300/U500 OpenOCD scriptsTim Newsome2-0/+2
2017-06-09Make HiFive1 testing (mostly) work againTim Newsome2-2/+5
Currently failing: DebugChangeString DebugFunctionCall InstantHaltTest
2017-06-09Fix using defaults for --server_cmd and --sim_cmdTim Newsome1-1/+1
2017-06-09Default to openocd, not riscv-openocdTim Newsome1-1/+1
AFAICT the normal build process never builds a binary called riscv-openocd.
2017-06-05Make pylint happy.Tim Newsome3-10/+13
If we want we can start using print(), but if so let's consistently use it instead of piecemeal. See also https://stackoverflow.com/questions/28694380/pylint-says-unnecessary-parens-after-r-keyword
2017-05-23Fail if simulator exits early.Richard Xia1-0/+6
2017-05-18debug: Correct the calling for a 32-bit simulation targetMegan Wachs1-1/+1
2017-05-17Shorten the debug testsPalmer Dabbelt1-4/+4
2017-05-17Merge pull request #49 from riscv/no_examine_targetPalmer Dabbelt1-1/+10
No Examine Target
2017-05-17Show the debug logs to stdout, to avoid travis timeoutsPalmer Dabbelt1-1/+1
2017-05-16debug: remove unused auto_int functionMegan Wachs1-3/+0
2017-05-16debug: Allow skipping the ExamineTarget task.Megan Wachs1-4/+9
2017-05-16debug: Allow skipping the ExamineTarget step by specifying misaMegan Wachs1-1/+8
2017-05-16Change Spike's RAM location to match the linker scriptPalmer Dabbelt1-2/+2
2017-05-16Link the infinate loop at 0x10000000Palmer Dabbelt3-1/+3
Spike appears to have a problem geterating DTS at 0x80000000.
2017-05-16Link in encoding.h instead of providing a path to itPalmer Dabbelt5-4/+5
2017-05-16debug: Update OpenOCD configs.Megan Wachs2-5/+4
2017-05-15Disable another PRIV mention, for nowPalmer Dabbelt1-1/+2
2017-05-15Disable the tests that touch PRIV, it's not implemented yetPalmer Dabbelt1-62/+63
2017-05-15Have the openocd invocation match the spike invocationPalmer Dabbelt1-1/+1
2017-05-15Disable some failing tests for nowPalmer Dabbelt1-37/+40
2017-05-15Don't rely on Spike's default ISAPalmer Dabbelt1-1/+3
2017-05-15Don't use the RTOS, and do "reset halt"Palmer Dabbelt1-3/+4
This is the most reliable way to run the tests for now.
2017-05-15Let Spike have the default amount of RAMPalmer Dabbelt1-1/+0
Without this programs won't run.
2017-05-15Don't build openocd here, it's in riscv-tools nowPalmer Dabbelt1-1/+5
2017-05-15debug: fix the make target for debug-checkMegan Wachs1-19/+2
2017-05-15debug: Use consistent 'sim_cmd' argument.Megan Wachs2-2/+2
2017-04-26Set FS before reading F registersPalmer Dabbelt1-0/+4
2017-04-18bump OpenOCD versionMegan Wachs1-1/+1
2017-04-18debug: Don't halt out of reset. It's unrealistic. Use a program which loops ↵Megan Wachs5-5/+20
(actually it just gets an exception anyway).
2017-04-18debug: Use RTOS OpenOCD for Spike for now.Megan Wachs1-1/+1
2017-04-17debug: Checkpoint restoring Spike functionalityMegan Wachs5-29/+51
2017-04-17Merge remote-tracking branch 'origin/newprogram' into debug-0.13Megan Wachs9-18/+42
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs6-6/+9
2017-04-14debug: checkpoint trying to get 64 bit programs to compile as well.Megan Wachs1-0/+3
2017-04-14debug: checkpoint of trying to get simulation tests workingMegan Wachs8-9/+29
2017-04-14debug: working with newprogram branchMegan Wachs4-10/+11
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