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2019-12-02Use a small binary to set up HiFive Unleashed. (#221)Tim Newsome3-10/+10
2019-11-22Move to Python 3. (#218)Tim Newsome4-75/+78
2019-10-15Add support to run all tests against HiFive Unleashed. (#212)Tim Newsome7-3/+191
2019-10-09Remove ocd_ prefix. (#210)Tim Newsome4-4/+4
2019-09-24Redo the debug README. (#205)Tim Newsome1-26/+19
2019-09-24Look for binaries in $PATH. (#208)Tim Newsome1-7/+4
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome4-19/+20
2019-07-15Make tests work with RV32E targets. (#196)Tim Newsome5-27/+45
2019-07-15Use work area in spike-1 to cover CRC algorithm. (#195)Tim Newsome2-1/+6
2019-06-14Work better with mainline gdb (#192)Tim Newsome2-23/+46
2019-05-16Cover with/without halt groups. (#191)Tim Newsome5-12/+20
2019-04-08Test lack of abstract CSR access. (#187)Tim Newsome7-8/+14
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome9-31/+51
2019-03-11Add SmpSimultaneousRunHalt test. (#181)Tim Newsome4-10/+89
2019-02-14Test `-rtos hwthread` (#178)Tim Newsome6-22/+81
2019-01-25Merge pull request #175 from riscv/test_rtiCarsten Gosvig7-7/+17
2019-01-07Fail on unsupported SREC type.Tim Newsome1-0/+2
2018-12-31Add testing of run-test/idle cases.Tim Newsome7-7/+17
2018-12-31Fix MemTestBlockTim Newsome1-20/+41
2018-12-03Reduce download size a bit.Tim Newsome2-6/+9
2018-11-30Use more than 1KB for download test.Tim Newsome1-1/+1
2018-11-16Make pylint happy.Tim Newsome1-3/+6
2018-11-14Merge pull request #165 from riscv/flashTim Newsome7-18/+103
2018-11-14Cleanup and renamed test flag to invalid_memory_returns_zerocgsfv4-6/+6
2018-11-13Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fixcgsfv4-2/+59
2018-11-12Simpler/more idiomatic way to keep string on stackTim Newsome1-4/+1
2018-10-31Add HiFive1-flash target configuration.Tim Newsome2-0/+59
2018-10-31Fix remaining tests to work from flash:Tim Newsome2-6/+17
2018-10-29Almost all tests pass with HiFive1-flashTim Newsome2-4/+13
2018-10-29Tweak debug tests to run out of flash.Tim Newsome4-8/+17
2018-10-24Merge branch 'TriggerLoadAddressInstant'Tim Newsome1-12/+1
2018-10-24Re-enable TriggerStoreAddressInstantTim Newsome1-12/+1
2018-10-05Make HwWatchpoint test fail on incorrect result.hw_watchpointTim Newsome3-7/+10
2018-10-03Added tests for hw and sw watchpointscgsfv3-0/+88
2018-09-13Assert if HiFive1 program is too large.Tim Newsome1-0/+2
2018-09-13Put debug test stack in data instead of textTim Newsome1-0/+1
2018-09-03Merge pull request #156 from riscv/PrivChangeTim Newsome1-27/+26
2018-08-31Fix CustomRegisterTest.Tim Newsome2-5/+6
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome12-0/+55
2018-08-28Reset address translation/perms before PrivChangeTim Newsome1-27/+26
2018-08-27Neuter TriggerStoreAddressInstantTim Newsome1-1/+13
2018-08-27Make pylint happy.Tim Newsome1-1/+2
2018-08-25Temporarily disabling PrivChange testAndrew Waterman1-22/+23
2018-08-23Make pylint happy with change d1d2d953b5016b465.Tim Newsome2-3/+4
2018-08-23Get all of the log into the final log fileTim Newsome1-6/+20
2018-08-23Merge pull request #153 from dmitryryzhov/rtos-switch-active-threadTim Newsome1-0/+28
2018-08-22Disable MulticoreRunHaltStepiTestTim Newsome1-52/+52
2018-08-22Add debug test, which checks that openocd correctly switch active thread on a...Dmitry Ryzhov1-0/+28
2018-08-13Add jump/hbreak test.Tim Newsome1-0/+23
2018-07-03rwatch/watch on explicit addressTim Newsome1-2/+4
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