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2019-10-15Add support to run all tests against HiFive Unleashed. (#212)Tim Newsome5-0/+184
* Parse inf/nan floats. * Enable mstatus.fs in SimpleF18Test Also accept "unable to fetch" message when FPRs aren't supported. * Add config files for HiFive Unleashed. * Add configs to flash HiFive Unleashed. All tests pass.
2019-10-09Remove ocd_ prefix. (#210)Tim Newsome4-4/+4
The latest OpenOCD doesn't need (nor support) this anymore.
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome1-1/+3
* Let the debugger enable mstatus.F if necessary. * Ignore (some) gdb debug output. * Increase timeout. * Make newer version of pylint happy.
2019-07-15Use work area in spike-1 to cover CRC algorithm. (#195)Tim Newsome1-0/+2
2019-05-16Cover with/without halt groups. (#191)Tim Newsome4-5/+6
Also work with the new command line options that were renamed in https://github.com/riscv/riscv-isa-sim/pull/299
2019-04-08Test lack of abstract CSR access. (#187)Tim Newsome6-6/+9
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome4-5/+11
Passes on spike and Arty. Won't merge until https://github.com/riscv/riscv-openocd/pull/364 merges.
2019-02-14Test `-rtos hwthread` (#178)Tim Newsome3-0/+57
* WIP * Use hwthread everywhere. * Test `-rtos hwthread`. Also tweak timeouts a bit so that we don't have ridiculous timeouts for simple operations. * Tweak timeouts so tests pass on a loaded system.
2018-12-31Add testing of run-test/idle cases.Tim Newsome6-6/+7
2018-11-14Merge pull request #165 from riscv/flashTim Newsome2-0/+59
Tweak debug tests to run out of flash.
2018-11-14Cleanup and renamed test flag to invalid_memory_returns_zerocgsfv2-2/+2
2018-11-13Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fixcgsfv2-2/+4
2018-10-31Add HiFive1-flash target configuration.Tim Newsome2-0/+59
2018-09-13Assert if HiFive1 program is too large.Tim Newsome1-0/+2
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome9-0/+9
Only works against spike, where I've implemented some custom debug registers to test against.
2018-04-19Delete E300Sim.pydebug-delete-simMegan Wachs1-17/+0
This file is wrong (the .cfg file isn't right) and not used by anything.
2018-04-02Use `gdb_report_register_access_error enable`Tim Newsome4-0/+6
2018-03-27Test debug authentication.Tim Newsome3-3/+18
Also halt instead of reset spike targets, which tests a more complicated code path.
2018-03-01Test debugging with/without a program bufferTim Newsome3-3/+3
2018-03-01Ensure an error when reading a non-existent CSR.Tim Newsome4-0/+16
2018-02-07Link scripts shouldn't be executable.Tim Newsome1-0/+0
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome4-4/+6
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
2017-10-24Increase dual-core RV64 timeouts.Tim Newsome2-2/+2
I need this for CompareSections to pass when I instrument spike to be really slow.
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome9-4/+48
The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them.
2017-09-21Add coverage for single-core non-rtos OpenOCD.Tim Newsome4-3/+19
2017-09-19Allow multiple reset vectors.Tim Newsome2-2/+2
Some boards have jumpers that control the reset vector, and forcing them one way or another is more annoying than dealing with it in software.
2017-09-01Use 32-bit link script for 32-bit target.Tim Newsome1-1/+1
2017-08-28This file isn't ready yet.Tim Newsome1-11/+0
2017-08-28Increase remotetimeout for spike targets.Tim Newsome5-0/+15
On overloaded systems, when executing compare-sections, otherwise gdb might hit a timeout and the compare-sections code doesn't deal with it. (You get an error message complaining that 130 is not a valid hex digit.)
2017-08-28Make pylint happy.Tim Newsome3-3/+3
2017-08-28WIP multicore testing.Tim Newsome4-0/+8
2017-08-28Make the debug tests aware of multicore.Tim Newsome11-38/+63
Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-08-10Give these sim targets a chance of passing.Tim Newsome2-3/+7
Also make sure vsim.log makes it into the generated log file.
2017-06-26Move target definition into individual files.Tim Newsome21-148/+74
Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.
2017-06-15Test 64-bit addressing.Tim Newsome4-0/+53
The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000. Also a minor change to log file naming so that 'make all' works again. I'll fix this better later.
2017-06-09Add final echo to E300/U500 OpenOCD scriptsTim Newsome2-0/+2
2017-06-09Make HiFive1 testing (mostly) work againTim Newsome2-2/+5
Currently failing: DebugChangeString DebugFunctionCall InstantHaltTest
2017-05-16Link the infinate loop at 0x10000000Palmer Dabbelt1-1/+1
Spike appears to have a problem geterating DTS at 0x80000000.
2017-05-16debug: Update OpenOCD configs.Megan Wachs2-5/+4
2017-05-15Don't use the RTOS, and do "reset halt"Palmer Dabbelt1-3/+4
This is the most reliable way to run the tests for now.
2017-04-18debug: Don't halt out of reset. It's unrealistic. Use a program which loops ↵Megan Wachs1-1/+2
(actually it just gets an exception anyway).
2017-04-18debug: Use RTOS OpenOCD for Spike for now.Megan Wachs1-1/+1
2017-04-17Merge remote-tracking branch 'origin/newprogram' into debug-0.13Megan Wachs5-7/+10
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs5-5/+5
2017-04-14debug: checkpoint of trying to get simulation tests workingMegan Wachs5-5/+7
2017-04-14debug: working with newprogram branchMegan Wachs2-3/+4
2017-03-29Change the global pointer symbol to __global_pointer$Palmer Dabbelt5-5/+5
This changed a while ago in binutils.
2017-03-03Resurrect spike debug supportPalmer Dabbelt1-0/+17
2017-02-17Add HiFive1 target.Tim Newsome2-0/+57
2016-10-18Pull port number from VCS output and pass to OpenOCD.Richard Xia2-0/+2
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