riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2019-10-09	Remove ocd_ prefix. (#210)	Tim Newsome	4	-4/+4
	The latest OpenOCD doesn't need (nor support) this anymore.
2019-08-02	Miscellaneous minor test improvements (#199)	Tim Newsome	1	-1/+3
	* Let the debugger enable mstatus.F if necessary. * Ignore (some) gdb debug output. * Increase timeout. * Make newer version of pylint happy.
2019-07-15	Use work area in spike-1 to cover CRC algorithm. (#195)	Tim Newsome	1	-0/+2

2019-05-16	Cover with/without halt groups. (#191)	Tim Newsome	4	-5/+6
	Also work with the new command line options that were renamed in https://github.com/riscv/riscv-isa-sim/pull/299
2019-04-08	Test lack of abstract CSR access. (#187)	Tim Newsome	6	-6/+9

2019-04-04	Test simultaneous resume using hasel. (#186)	Tim Newsome	4	-5/+11
	Passes on spike and Arty. Won't merge until https://github.com/riscv/riscv-openocd/pull/364 merges.
2019-02-14	Test `-rtos hwthread` (#178)	Tim Newsome	3	-0/+57
	* WIP * Use hwthread everywhere. * Test `-rtos hwthread`. Also tweak timeouts a bit so that we don't have ridiculous timeouts for simple operations. * Tweak timeouts so tests pass on a loaded system.
2018-12-31	Add testing of run-test/idle cases.	Tim Newsome	6	-6/+7

2018-08-29	Add test case for `riscv expose_custom`.	Tim Newsome	9	-0/+9
	Only works against spike, where I've implemented some custom debug registers to test against.
2018-04-02	Use `gdb_report_register_access_error enable`	Tim Newsome	3	-0/+3

2018-03-27	Test debug authentication.	Tim Newsome	3	-3/+18
	Also halt instead of reset spike targets, which tests a more complicated code path.
2018-03-01	Test debugging with/without a program buffer	Tim Newsome	3	-3/+3

2018-03-01	Ensure an error when reading a non-existent CSR.	Tim Newsome	3	-0/+12

2017-12-27	Test FPRs that aren't XLEN in size.	Tim Newsome	4	-4/+6
	Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
2017-10-24	Increase dual-core RV64 timeouts.	Tim Newsome	2	-2/+2
	I need this for CompareSections to pass when I instrument spike to be really slow.
2017-09-29	Fix tests to work in multi-gdb mode.	Tim Newsome	9	-4/+48
	The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them.
2017-09-21	Add coverage for single-core non-rtos OpenOCD.	Tim Newsome	4	-3/+19

2017-09-19	Allow multiple reset vectors.	Tim Newsome	2	-2/+2
	Some boards have jumpers that control the reset vector, and forcing them one way or another is more annoying than dealing with it in software.
2017-09-01	Use 32-bit link script for 32-bit target.	Tim Newsome	1	-1/+1

2017-08-28	This file isn't ready yet.	Tim Newsome	1	-11/+0

2017-08-28	Increase remotetimeout for spike targets.	Tim Newsome	5	-0/+15
	On overloaded systems, when executing compare-sections, otherwise gdb might hit a timeout and the compare-sections code doesn't deal with it. (You get an error message complaining that 130 is not a valid hex digit.)
2017-08-28	Make pylint happy.	Tim Newsome	2	-2/+2

2017-08-28	WIP multicore testing.	Tim Newsome	2	-0/+4

2017-08-28	Make the debug tests aware of multicore.	Tim Newsome	6	-25/+35
	Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-06-26	Move target definition into individual files.	Tim Newsome	6	-0/+132
	Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.