riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2019-07-15	Make tests work with RV32E targets. (#196)	Tim Newsome	1	-0/+2

2018-10-29	Tweak debug tests to run out of flash.	Tim Newsome	1	-0/+1
	Not all tests pass when run out of flash yet, but it's getting a lot closer. The ones still failing on HiFive1-flash are: DebugSymbols, Hwbp2, InstantHaltTest, TriggerDmode, TriggerLoadAddressInstant, and TriggerStoreAddressInstant.
2017-05-16	Link in encoding.h instead of providing a path to it	Palmer Dabbelt	1	-1/+1

2016-12-07	Use our own XLEN macro.	Tim Newsome	1	-1/+1
	Relying on something that the compiler automatically sets is apparently not reliable.
2016-12-06	avoid non-standard predefined macros	Andrew Waterman	1	-1/+1

2016-07-18	Add simple register tests.	Tim Newsome	1	-30/+31
	Make the RegsTest case a bit more comprehensible.
2016-07-18	Add block test.	Tim Newsome	1	-1/+1

2016-07-18	All tests pass with spike now.	Tim Newsome	1	-1/+4
	I did comment out a couple.
2016-07-18	Made some progress towards working with spike.	Tim Newsome	1	-30/+40
	I'm writing all the tests so they should just work on real hardware, too.
2016-07-18	WIP on debug testing.	Tim Newsome	1	-0/+43
	./gdbserver.py --m2gl_m2s --openocd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl" -- RegsTest.test_write_gprs doesn't fail in a completely crazy way.