Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2018-10-24 | Merge branch 'TriggerLoadAddressInstant' | Tim Newsome | 1 | -12/+1 | |
2018-10-24 | Re-enable TriggerStoreAddressInstant | Tim Newsome | 1 | -12/+1 | |
Gdb and OpenOCD were fixed so we don't have to accept broken behavior anymore. | |||||
2018-10-05 | Make HwWatchpoint test fail on incorrect result.hw_watchpoint | Tim Newsome | 1 | -5/+8 | |
Also tiny cleanups, making pylint happy. | |||||
2018-10-03 | Added tests for hw and sw watchpoints | cgsfv | 1 | -0/+56 | |
2018-09-03 | Merge pull request #156 from riscv/PrivChange | Tim Newsome | 1 | -27/+26 | |
Reset address translation/perms before PrivChange | |||||
2018-08-31 | Fix CustomRegisterTest. | Tim Newsome | 1 | -1/+2 | |
gdb in riscv-tools doesn't automatically create a "custom" group like mainline gdb does. | |||||
2018-08-29 | Add test case for `riscv expose_custom`. | Tim Newsome | 1 | -0/+30 | |
Only works against spike, where I've implemented some custom debug registers to test against. | |||||
2018-08-28 | Reset address translation/perms before PrivChange | Tim Newsome | 1 | -27/+26 | |
We already did this for PrivTest. Hopefully solves #155, but I haven't been able to reproduce it. | |||||
2018-08-27 | Neuter TriggerStoreAddressInstant | Tim Newsome | 1 | -1/+13 | |
Now that OpenOCD can tell gdb exactly which watchpoint was hit, this test exposes another problem: https://github.com/riscv/riscv-openocd/issues/295 For now neuter the test so the testsuite can still be useful. | |||||
2018-08-27 | Make pylint happy. | Tim Newsome | 1 | -1/+2 | |
2018-08-25 | Temporarily disabling PrivChange test | Andrew Waterman | 1 | -22/+23 | |
@timsifive we are debugging intermittent failures. | |||||
2018-08-23 | Make pylint happy with change d1d2d953b5016b465. | Tim Newsome | 1 | -2/+3 | |
2018-08-23 | Merge pull request #153 from dmitryryzhov/rtos-switch-active-thread | Tim Newsome | 1 | -0/+28 | |
Add debug test, which checks that openocd correctly switch active thread on any hart halt. | |||||
2018-08-22 | Disable MulticoreRunHaltStepiTest | Tim Newsome | 1 | -52/+52 | |
It's failing (intermittently?). See eg. https://travis-ci.org/riscv/riscv-tools/builds/418928412?utm_source=github_status&utm_medium=notification | |||||
2018-08-22 | Add debug test, which checks that openocd correctly switch active thread on ↵ | Dmitry Ryzhov | 1 | -0/+28 | |
any hart halt. | |||||
2018-08-13 | Add jump/hbreak test. | Tim Newsome | 1 | -0/+23 | |
2018-07-03 | rwatch/watch on explicit address | Tim Newsome | 1 | -2/+4 | |
Newer gdb requires more debug info in order to "watch data" in this test. I'm not sure how to make that debug info happen, so instead we tell it the address to use. | |||||
2018-05-18 | Fix MulticoreRunHaltStepiTest | Tim Newsome | 1 | -19/+37 | |
The test actually wasn't checking interrupt counts at all. Fixing it required some other changes: Make sure all harts get to run Add some retries, since on a loaded machine against spike both harts might not get to run, even if you give spike a generous amount of time to do so. | |||||
2018-05-14 | Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-single | Megan Wachs | 1 | -17/+4 | |
2018-05-14 | Make DownloadTest properly park other harts. | Tim Newsome | 1 | -1/+2 | |
2018-05-14 | debug: remove some unintentionally added newlines | Megan Wachs | 1 | -2/+0 | |
2018-05-14 | debug: Fixing the non-RTOS behavior for DownloadTest | Megan Wachs | 1 | -7/+16 | |
2018-05-11 | debug: mark more tests as single-hart tests | Megan Wachs | 1 | -6/+13 | |
2018-04-30 | Fix formatting to make pylint happy. | Tim Newsome | 1 | -5/+6 | |
2018-04-27 | debug: need to clear satp before changing privdebug-clear-satp | Megan Wachs | 1 | -0/+7 | |
ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness. | |||||
2018-04-09 | Compute gdb command timeout based on ops estimate | Tim Newsome | 1 | -1/+1 | |
The caller of gdb.command() should estimate how much work gdb needs to do, and testlib then scales this up proportional to the general gdb timeout we configured. This hopefully allows us to configure a tighter timeout, so we don't have to have a multi-hour timeout just for something that takes long like `load` on a really slow simulator. Hopefully this addresses #122. | |||||
2018-03-01 | Ensure an error when reading a non-existent CSR. | Tim Newsome | 1 | -0/+13 | |
2018-02-09 | Test resuming from a trigger.resume_from_trigger | Tim Newsome | 1 | -0/+5 | |
2018-01-08 | Deal with gdb reporting pmpcfg0 not existing. | Tim Newsome | 1 | -3/+7 | |
It's an optional register. | |||||
2018-01-05 | Add test for multicore failure | Tim Newsome | 1 | -0/+28 | |
Specifically, make sure that after resuming all cores, and halting core 0, that OpenOCD's poll() doesn't mess up the currently selected hart to the point where memory accesses intended for core 0 go to core 1. | |||||
2017-12-27 | Test FPRs that aren't XLEN in size. | Tim Newsome | 1 | -0/+6 | |
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110 | |||||
2017-12-20 | Verify that F18 does not exist on FPU-less targets | Tim Newsome | 1 | -17/+20 | |
2017-12-01 | Ensure there are no unnamed registers. | Tim Newsome | 1 | -0/+2 | |
2017-11-19 | Make pylint happy. | Tim Newsome | 1 | -1/+2 | |
2017-11-16 | Debug: Use the --32 and --64 command line arguments (#97) | Megan Wachs | 1 | -4/+0 | |
* Debug: Actually use the --32 and --64 command line arguments * debug: make XLEN mismatch message clearer | |||||
2017-11-16 | Disable PMP for PrivRw test. | Tim Newsome | 1 | -0/+5 | |
2017-11-15 | Clarify PrivTest detail. | Tim Newsome | 1 | -0/+2 | |
2017-11-02 | Add --print-log-names to print temp log names ASAP | Tim Newsome | 1 | -0/+2 | |
When not passed, they are no longer printed out. | |||||
2017-11-01 | Make pylint 1.6.5 happy. | Tim Newsome | 1 | -1/+1 | |
2017-11-01 | Test register aliases in the simple register tests | Tim Newsome | 1 | -9/+17 | |
2017-11-01 | Fix MulticoreRegTest. | Tim Newsome | 1 | -58/+54 | |
This test would fail intermittently if gdb on the first hart managed to set a breakpoint, resume, halt, and clear the breakpoint before the second hart got a chance to resume. | |||||
2017-10-31 | Temporarily comment out MulticoreRegTest due to flakiness. | Richard Xia | 1 | -57/+58 | |
2017-10-19 | Get helpful gdb output in MemTestBlock. | Tim Newsome | 1 | -1/+4 | |
2017-10-04 | Resurrect priv tests. | Tim Newsome | 1 | -52/+51 | |
2017-09-29 | Fix tests to work in multi-gdb mode. | Tim Newsome | 1 | -12/+17 | |
The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them. | |||||
2017-09-19 | Allow multiple reset vectors. | Tim Newsome | 1 | -1/+1 | |
Some boards have jumpers that control the reset vector, and forcing them one way or another is more annoying than dealing with it in software. | |||||
2017-09-18 | Add interrupts to MulticoreRunHaltStepiTest. | Tim Newsome | 1 | -1/+8 | |
Just to hammer on anything at once, and hopefully catch weird interactions if they exist. | |||||
2017-09-14 | Test debugging code with interrupts. | Tim Newsome | 1 | -0/+43 | |
2017-09-01 | Add some infrastructure for multicore tests. | Tim Newsome | 1 | -1/+1 | |
When compiling, define the number of harts. This means we only need to allocate a lot of stack if there are a lot of harts. | |||||
2017-08-28 | Make MemTestBlock output a more descriptive error. | Tim Newsome | 1 | -11/+15 | |