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2022-12-28Fix ma_fetch test to support systems where no RVC does not imply IALIGN=32Jerry Zhao1-9/+31
2022-12-28Fix clean in isa/ with non-default compiler (#443)Alex Shpilkin1-1/+1
2022-12-27Merge pull request #442 from riscv-software-src/ceasetestTim Newsome2-3/+60
2022-12-14debug: Add CeaseRunTestTim Newsome1-0/+23
2022-12-14debug: Add CeaseStepiTest.Tim Newsome2-3/+37
2022-12-14debug: Create CeaseMultiTest. (#436)Tim Newsome2-2/+55
2022-12-14debug: Remove unnecessary exit() functions. (#437)Tim Newsome3-11/+4
2022-12-08Fix regression in VcsSim introduced by #334 (#440)Jerry Zhao1-0/+1
2022-12-07zicntr: separate cycle/instret accessibility test (#439)Chih-Min Chao5-16/+69
2022-12-01debug: Disassemble memory when a failure happens. (#432)Tim Newsome1-1/+1
2022-12-01`flush regs` -> `maintenance flush register-cache` (#431)Tim Newsome1-1/+1
2022-12-01debug: Park unused harts with a cease instruction. (#434)Tim Newsome3-2/+23
2022-12-01Share exit() among more tests. (#433)Tim Newsome3-16/+9
2022-11-10SvNNTest needs 32KB of RAM. (#428)Tim Newsome2-4/+7
2022-11-04Make MulticoreRegTest work with real hardware.Tim Newsome2-17/+19
2022-11-03Fix PrivChange test address comparison. (#427)Tim Newsome1-3/+4
2022-10-26Specify trigger type=2 in trigger.S (#425)YenHaoChen1-2/+3
2022-10-24Increase timeouts for multi-spike test. (#423)Tim Newsome2-3/+4
2022-10-21Change memory address used in debug tests. (#422)Tim Newsome4-3/+3
2022-10-20Merge pull request #421 from riscv-software-src/pylintTim Newsome1-1/+2
2022-10-20Merge pull request #420 from riscv-software-src/test_fpr_progbufTim Newsome3-2/+9
2022-10-12Fix long line to make pylint happy.Tim Newsome1-1/+2
2022-10-12Get coverage of progbuf FPR accesses.Tim Newsome3-2/+9
2022-10-10Merge pull request #417 from riscv-software-src/debug_serverTim Newsome2-3/+14
2022-10-07debug: Add --debug_server arg to open gdb on OpenOCDTim Newsome2-3/+14
2022-10-06Merge pull request #414 from YenHaoChen/pr-timestampTim Newsome1-2/+2
2022-10-05Update testlib.py; remove ANSI escape sequencesYenHaoChen1-1/+2
2022-10-05update gdbserver.py; release tolerance value of MemorySampleTest()YenHaoChen1-2/+2
2022-09-27rv64ui test misaligned load/store data (#410)John Ingalls2-0/+388
2022-09-27zicboz: comment # (#412)John Ingalls1-1/+1
2022-09-26zicbo test zero (#411)John Ingalls3-2/+49
2022-07-25Ignore `mip` and `time` in DisconnectTest. (#406)Tim Newsome1-1/+2
2022-07-22Fix string formatting in testlib.assertTrue()Tim Newsome1-1/+1
2022-07-14Pylint fix. (#405)Tim Newsome1-1/+2
2022-07-14Only run SemihostingFileio on single hart systems. (#404)Tim Newsome1-0/+11
2022-07-11Debug MemorySampleMixed: Disable 64-bit sampling on 32-bit targets (#402)Luke Wren1-2/+6
2022-07-08Fix SemihostingFileio (#403)Tim Newsome1-1/+2
2022-07-01Complete this pass of pylint changes. (#401)Tim Newsome2-149/+151
2022-06-23Another pylint upgrade. (#398)Tim Newsome3-173/+191
2022-06-21Update information about Makefile fragments (#399)Mehmet Oguz Derin1-4/+2
2022-06-09Test misaligned stores. (#397)Tim Newsome8-0/+158
2022-06-08Merge pull request #395 from riscv-software-src/misaligned_storeAndrew Waterman10-6/+164
2022-06-08Test semihosting_fileioTim Newsome2-4/+27
2022-06-07Test misaligned loads.Tim Newsome8-0/+160
2022-06-07Set TESTNUM before executing code.Tim Newsome3-6/+4
2022-06-06Revert unaligned tests.Tim Newsome3-51/+1
2022-06-06Test unaligned ld accesses.Tim Newsome1-0/+27
2022-06-06Add unaligned test cases for lwTim Newsome1-0/+23
2022-06-06Set TESTNUM before executing code.Tim Newsome1-1/+1
2022-05-31Address pylint warnings. (#385)Tim Newsome8-15/+16
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