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2023-02-21
debug: fix pylint error W0621 redefined-outer-name
Chao Du
1
-2
/
+2
2023-02-16
Add test for icount triggers.
Tim Newsome
1
-0
/
+27
2023-02-15
Merge pull request #451 from riscv-software-src/etrigger_fix
Tim Newsome
1
-0
/
+1
2023-02-13
Fix ma_fetch test for norvc (#454)
Yujia Qiao
1
-1
/
+1
2023-02-13
Update register name to satp (#455)
Pascal Cotret
1
-1
/
+1
2023-02-03
env: update commit hash for submodule env (#452)
deepak0414
1
-0
/
+0
2023-02-02
Fix EtriggerTest on multi-hart targets.
Tim Newsome
1
-0
/
+1
2023-01-19
Fix ma_fetch test for writable misa.C (#449)
Jerry Zhao
1
-3
/
+3
2023-01-19
Pass --misaligned flag to Spike to run ISA tests (#445)
Andrew Waterman
1
-2
/
+2
2023-01-06
Merge pull request #446 from riscv-software-src/itrigger
Tim Newsome
2
-1
/
+30
2023-01-06
debug: Add Itrigger test.
Tim Newsome
1
-0
/
+26
2023-01-06
debug: Tweak interrupt.c, so a test can run to exit()
Tim Newsome
1
-1
/
+4
2023-01-06
Merge pull request #447 from riscv-software-src/etrigger
Tim Newsome
2
-1
/
+20
2022-12-29
Merge branch 'jerryz123-fix-ma_fetch'
Andrew Waterman
1
-9
/
+31
2022-12-29
debug: Add etrigger test.
Tim Newsome
2
-1
/
+20
2022-12-28
Fix ma_fetch test to support systems where no RVC does not imply IALIGN=32
Jerry Zhao
1
-9
/
+31
2022-12-28
Fix clean in isa/ with non-default compiler (#443)
Alex Shpilkin
1
-1
/
+1
2022-12-27
Merge pull request #442 from riscv-software-src/ceasetest
Tim Newsome
2
-3
/
+60
2022-12-14
debug: Add CeaseRunTest
Tim Newsome
1
-0
/
+23
2022-12-14
debug: Add CeaseStepiTest.
Tim Newsome
2
-3
/
+37
2022-12-14
debug: Create CeaseMultiTest. (#436)
Tim Newsome
2
-2
/
+55
2022-12-14
debug: Remove unnecessary exit() functions. (#437)
Tim Newsome
3
-11
/
+4
2022-12-08
Fix regression in VcsSim introduced by #334 (#440)
Jerry Zhao
1
-0
/
+1
2022-12-07
zicntr: separate cycle/instret accessibility test (#439)
Chih-Min Chao
5
-16
/
+69
2022-12-01
debug: Disassemble memory when a failure happens. (#432)
Tim Newsome
1
-1
/
+1
2022-12-01
`flush regs` -> `maintenance flush register-cache` (#431)
Tim Newsome
1
-1
/
+1
2022-12-01
debug: Park unused harts with a cease instruction. (#434)
Tim Newsome
3
-2
/
+23
2022-12-01
Share exit() among more tests. (#433)
Tim Newsome
3
-16
/
+9
2022-11-10
SvNNTest needs 32KB of RAM. (#428)
Tim Newsome
2
-4
/
+7
2022-11-04
Make MulticoreRegTest work with real hardware.
Tim Newsome
2
-17
/
+19
2022-11-03
Fix PrivChange test address comparison. (#427)
Tim Newsome
1
-3
/
+4
2022-10-26
Specify trigger type=2 in trigger.S (#425)
YenHaoChen
1
-2
/
+3
2022-10-24
Increase timeouts for multi-spike test. (#423)
Tim Newsome
2
-3
/
+4
2022-10-21
Change memory address used in debug tests. (#422)
Tim Newsome
4
-3
/
+3
2022-10-20
Merge pull request #421 from riscv-software-src/pylint
Tim Newsome
1
-1
/
+2
2022-10-20
Merge pull request #420 from riscv-software-src/test_fpr_progbuf
Tim Newsome
3
-2
/
+9
2022-10-12
Fix long line to make pylint happy.
Tim Newsome
1
-1
/
+2
2022-10-12
Get coverage of progbuf FPR accesses.
Tim Newsome
3
-2
/
+9
2022-10-10
Merge pull request #417 from riscv-software-src/debug_server
Tim Newsome
2
-3
/
+14
2022-10-07
debug: Add --debug_server arg to open gdb on OpenOCD
Tim Newsome
2
-3
/
+14
2022-10-06
Merge pull request #414 from YenHaoChen/pr-timestamp
Tim Newsome
1
-2
/
+2
2022-10-05
Update testlib.py; remove ANSI escape sequences
YenHaoChen
1
-1
/
+2
2022-10-05
update gdbserver.py; release tolerance value of MemorySampleTest()
YenHaoChen
1
-2
/
+2
2022-09-27
rv64ui test misaligned load/store data (#410)
John Ingalls
2
-0
/
+388
2022-09-27
zicboz: comment # (#412)
John Ingalls
1
-1
/
+1
2022-09-26
zicbo test zero (#411)
John Ingalls
3
-2
/
+49
2022-07-25
Ignore `mip` and `time` in DisconnectTest. (#406)
Tim Newsome
1
-1
/
+2
2022-07-22
Fix string formatting in testlib.assertTrue()
Tim Newsome
1
-1
/
+1
2022-07-14
Pylint fix. (#405)
Tim Newsome
1
-1
/
+2
2022-07-14
Only run SemihostingFileio on single hart systems. (#404)
Tim Newsome
1
-0
/
+11
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