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AgeCommit message (Expand)AuthorFilesLines
2014-04-03Sync env with opcodesStephen Twigg1-5/+5
2014-03-25Make qsort input size more reasonableAndrew Waterman1-1539/+105
2014-03-25Make qsort benchmark more meaningfulAndrew Waterman4-96/+1722
2014-03-18Check FP corner cases and flagsAndrew Waterman7-183/+210
2014-03-06Add fclass.{s|d} testAndrew Waterman2-1/+58
2014-03-03update envYunsup Lee1-5/+5
2014-03-02push envYunsup Lee1-5/+5
2014-03-02add vfmsv.{s,d} testsYunsup Lee3-5/+60
2014-02-27push envYunsup Lee1-5/+5
2014-02-27add keepcfg testYunsup Lee2-1/+84
2014-02-26test to see whether vector unit is able to take 2 fmas in parallelYunsup Lee2-1/+181
2014-02-25push envYunsup Lee1-5/+5
2014-02-22Sort fixes: support for repeated trials.Eric Love3-35/+65
2014-02-20Merge commit '0661b47765081c710af3df66ec698aa58ff14d5d'Eric Love6-0/+2501
2014-02-20Added TAV sort benchmarksEric Love6-0/+2501
2014-02-11Run benchmarks in user modeAndrew Waterman3-49/+186
2014-02-11Merge branch 'master' of github.com:ucb-bar/riscv-testsAdam Izraelevitz199-1298/+5346
2014-02-11Updated README to recursively initialize reposAdam Izraelevitz1-0/+1
2014-02-10Revert to old AUIPC definitionAndrew Waterman3-21/+13
2014-02-06with env as a submodule, now have to populate itScott Beamer1-0/+1
2014-02-06fix recursive interrupts, and more improvements to codeYunsup Lee1-5/+5
2014-02-06Improve VM trap entry codeAndrew Waterman1-5/+5
2014-02-06Clean up benchmarks; support uarch-specific countersAndrew Waterman31-1026/+352
2014-02-06push envYunsup Lee1-5/+5
2014-02-04Add Stephen's vector FFT codeQuan Nguyen17-1/+1164
2014-02-03Add vfmsv instruction test, change vsetprec to vsetucfgQuan Nguyen3-2/+58
2014-01-31Shrink hex dumpsAndrew Waterman27-28/+2
2014-01-31Add rv32si tests, including illegality of shamt[5]Andrew Waterman8-15/+95
2014-01-31Minor Makefile improvementsHenry Cook2-3/+3
2014-01-31Make CSR test much more robustAndrew Waterman1-0/+52
2014-01-31Reference TESTNUM instead of x28 directlyAndrew Waterman69-217/+217
2014-01-23Done with rv32ui asm test portsEric Love1-2/+2
2014-01-23Fixed srl, srliEric Love3-25/+35
2014-01-23srl and sraiEric Love3-33/+33
2014-01-23First round of rv32ui asm testsEric Love50-15/+3410
2014-01-21Add CSRRx/CSRRxI testAndrew Waterman3-1/+35
2014-01-20Add packed vvadd test for confprec HwachaQuan Nguyen2-0/+106
2014-01-20Push envQuan Nguyen1-5/+5
2014-01-16Make LR/SC test more thoroughAndrew Waterman2-24/+37
2014-01-13Update v envAndrew Waterman1-5/+5
2013-11-28Fix load offsets for the vvadd_fw testAlbert Ou1-3/+3
2013-11-25Update benchmarks to new privileged ISAAndrew Waterman9-164/+38
2013-11-24Update to new privileged ISAAndrew Waterman17-88/+95
2013-11-19Add rv64uv-p-amoxor_{w,d} testsQuan Nguyen3-2/+118
2013-11-19fix rv64uv/vvadd_fd test to correctly check resultsYunsup Lee1-2/+2
2013-11-13added riscv-test-env as a submoduleYunsup Lee2-0/+8
2013-11-13split out envs from riscv-testsYunsup Lee12-1200/+0
2013-11-05add accelerator disabled causeYunsup Lee1-0/+1
2013-11-05correctly set SR_EA bit for all vector physical supervisor testsYunsup Lee12-0/+14
2013-11-05correctly set SR_EA bit for all vector physical testsYunsup Lee61-61/+64
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