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2017-08-28Fix MemTest* after sloppy rebase.Tim Newsome1-2/+2
2017-08-28Rename test to MulticoreRunHaltStepiTest.Tim Newsome1-1/+1
2017-08-28Make pylint happy.Tim Newsome3-3/+3
2017-08-28WIP multicore testing.Tim Newsome7-18/+95
2017-08-28WIP towards multiple gdb instances.Tim Newsome1-4/+14
2017-08-28Make the debug tests aware of multicore.Tim Newsome17-189/+267
Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-08-28Increase delay in UserInterrupt.Tim Newsome1-1/+1
When a machine is very loaded, otherwise it could happen that we send the interrupt before the resume has actually happened.
2017-08-16Merge pull request #67 from riscv/sfence_vmaPalmer Dabbelt2-6/+9
Inform GCC that "sfence.vma" clobbers memory
2017-08-16Inform GCC that "sfence.vma" clobbers memoryPalmer Dabbelt2-6/+9
2017-08-14Put logfile code back so everything works again.Tim Newsome2-4/+5
I don't exactly understand why it has to be the way it is, but I just want it to work. Also fix a pylint complaint.
2017-08-14Merge pull request #66 from riscv/debug_user_nicenessMegan Wachs2-6/+14
Debug: Usability Features
2017-08-14debug: clean up Temporary Log File messagesMegan Wachs1-2/+2
2017-08-14debug: Avoid None type errorMegan Wachs1-1/+1
2017-08-14debug: Revert change to print backtrace, as that is actually already printedMegan Wachs1-2/+0
2017-08-14debug: Allow OpenOCD startup timeout to be specified. Print out path to log ↵Megan Wachs2-5/+13
files.
2017-08-14When a test fails with exception, actually print out the reason why.Megan Wachs1-0/+2
2017-08-13Make MemTest* catch reading too many words.Tim Newsome1-7/+6
For one of the test addresses, use the highest possible one to ensure that OpenOCD isn't secretly reading/writing more words than requested.
2017-08-11Show the OpenOCD log in all(?) failure cases.Tim Newsome1-23/+29
2017-08-11Print out name of logfile when debug test is run.Tim Newsome1-5/+5
2017-08-11When make fails to run a test, print out the log.Tim Newsome2-2/+6
2017-08-11Don't use `set pipefail` which is a bashism.Tim Newsome1-7/+5
Instead, just give up on making the log files altogether now. Since gdbserver.py makes its own log files it's not as necessary in any case. This is yet another commit in an attempt to get the riscv-tools build to actually fail if these tests fail.
2017-08-11Don't eat errors in debug Makefile.Tim Newsome1-0/+1
2017-08-10Don't run debug tests as part of build.Tim Newsome2-4/+3
Testing is a separate step. Also fix Issue #64 by adding src_dir to the path to the targets file.
2017-08-10Pylint target files as well.Tim Newsome2-2/+2
This would have prevented some bugs I committed earlier.
2017-08-10Give these sim targets a chance of passing.Tim Newsome3-5/+11
Also make sure vsim.log makes it into the generated log file.
2017-08-08Merge pull request #62 from ↵Palmer Dabbelt1-1/+6
richardxia/only-emit-f-instructions-when-compiled-for-f rv64[ms]i-csr: Only emit F instructions when compiled for F.
2017-08-07rv64[ms]i-csr: Only emit F instructions when compiled for F.Richard Xia1-1/+6
2017-08-04RV32 div tests should use -2^31 for min value, not -2^63Andrew Waterman3-9/+9
2017-08-04Improve RVC testAndrew Waterman3-9/+9
Make the page-crossing instruction non-idempotent to detect erroneously executing the first 16 bits of the instruction with garbage MSBs.
2017-07-31Fix the end of MulticoreTest.Tim Newsome1-30/+22
Now it actually confirms that we're talking to two different cores which have different values in their registers. Previously it could have been fooled if eg. the thread command was a nop.
2017-07-27Make pylint happy.Tim Newsome1-2/+2
2017-07-26Use new OpenOCD messages to determine gdb port.Tim Newsome1-41/+8
This is simpler and more reliable than playing around with lsof. Specifically, it works if the OpenOCD command is "strace openocd" while the previous code did not.
2017-07-21Only clean up logfiles that we know we created.Tim Newsome1-1/+1
2017-07-20Add back code to clean up triggers in entry.STim Newsome3-0/+24
Then for targets that can't handle this because they don't implement hmode, add a target setting that allows that to be specified.
2017-07-18Check all PCs after reset.Tim Newsome1-1/+7
2017-07-12Print out logs in more failure cases.Tim Newsome1-4/+10
2017-07-06Merge pull request #58 from riscv/fpga_reset_haltTim Newsome1-0/+5
debug: Make the 'out of reset' tests apply reset
2017-07-06debug: Make the 'out of reset' tests actually apply resetmwachs51-0/+5
2017-07-03Add gdb_setup to target for arbitrary gdb commandsTim Newsome2-0/+7
I'm using this for a target where misa is at an old address, to set riscv use_compressed_breakpoints off
2017-07-03Don't clear triggers during execution.Tim Newsome1-9/+0
This shouldn't affect triggers set by the debugger, because running code can't change those. When it does affect them, it breaks Hwbp1 which sets the breakpoint before running the program.
2017-06-27Tolerate missing misa register.Tim Newsome1-1/+7
At least in the test programs. There are other places where this causes trouble as well.
2017-06-27Merge pull request #55 from riscv/debugTim Newsome1-1/+1
Test gdb/OpenOCD during regular test run.
2017-06-27Merge pull request #56 from riscv/configTim Newsome26-284/+184
Move target definition into individual files.
2017-06-26Move target definition into individual files.Tim Newsome26-284/+184
Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.
2017-06-23Test gdb/OpenOCD during regular test run.Tim Newsome1-1/+1
2017-06-22Add basic multicore test.Tim Newsome3-42/+128
2017-06-20Smoketest multicore.Tim Newsome3-14/+55
When connecting to gdb, select a random thread and use that for the current test. Also replace infinite_loop with something that will later allow smoketesting of more than one thread.
2017-06-19Write OpenOCD log when it crashes early.Tim Newsome1-2/+4
2017-06-16Store logs for all tests in logs/Tim Newsome1-30/+58
This creates a record of passing as well as failing tests, and gets rid of the log clutter that you previously ended up with in the current directory.
2017-06-15Test 64-bit addressing.Tim Newsome8-29/+90
The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000. Also a minor change to log file naming so that 'make all' works again. I'll fix this better later.
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