| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2017-06-09 | Add final echo to E300/U500 OpenOCD scripts | Tim Newsome | 2 | -0/+2 | |
| 2017-06-09 | Make HiFive1 testing (mostly) work again | Tim Newsome | 2 | -2/+5 | |
| Currently failing: DebugChangeString DebugFunctionCall InstantHaltTest | |||||
| 2017-06-09 | Fix using defaults for --server_cmd and --sim_cmd | Tim Newsome | 1 | -1/+1 | |
| 2017-06-09 | Default to openocd, not riscv-openocd | Tim Newsome | 1 | -1/+1 | |
| AFAICT the normal build process never builds a binary called riscv-openocd. | |||||
| 2017-06-05 | Make pylint happy. | Tim Newsome | 3 | -10/+13 | |
| If we want we can start using print(), but if so let's consistently use it instead of piecemeal. See also https://stackoverflow.com/questions/28694380/pylint-says-unnecessary-parens-after-r-keyword | |||||
| 2017-05-25 | Merge pull request #53 from richardxia/fail-if-simulator-exits-early | Palmer Dabbelt | 1 | -0/+6 | |
| Fail if simulator exits early. | |||||
| 2017-05-23 | Fail if simulator exits early. | Richard Xia | 1 | -0/+6 | |
| 2017-05-22 | minNum -> minimumNumber | Andrew Waterman | 2 | -4/+16 | |
| 2017-05-18 | Merge pull request #52 from riscv/vcs_sim_cmd | Megan Wachs | 1 | -1/+1 | |
| debug: Correct the calling for a 32-bit simulation target | |||||
| 2017-05-18 | debug: Correct the calling for a 32-bit simulation target | Megan Wachs | 1 | -1/+1 | |
| 2017-05-17 | Manually assemble bad shift amount, since assembler rejects | Andrew Waterman | 1 | -1/+1 | |
| Resolves #51 | |||||
| 2017-05-17 | Shorten the debug tests | Palmer Dabbelt | 1 | -4/+4 | |
| 2017-05-17 | Merge pull request #49 from riscv/no_examine_target | Palmer Dabbelt | 1 | -1/+10 | |
| No Examine Target | |||||
| 2017-05-17 | Show the debug logs to stdout, to avoid travis timeouts | Palmer Dabbelt | 1 | -1/+1 | |
| 2017-05-16 | debug: remove unused auto_int function | Megan Wachs | 1 | -3/+0 | |
| 2017-05-16 | debug: Allow skipping the ExamineTarget task. | Megan Wachs | 1 | -4/+9 | |
| 2017-05-16 | debug: Allow skipping the ExamineTarget step by specifying misa | Megan Wachs | 1 | -1/+8 | |
| 2017-05-16 | Merge pull request #47 from riscv/debug-0.13 | Palmer Dabbelt | 21 | -188/+291 | |
| Debug 0.13 Tests | |||||
| 2017-05-16 | Change Spike's RAM location to match the linker script | Palmer Dabbelt | 1 | -2/+2 | |
| 2017-05-16 | Link the infinate loop at 0x10000000 | Palmer Dabbelt | 3 | -1/+3 | |
| Spike appears to have a problem geterating DTS at 0x80000000. | |||||
| 2017-05-16 | Link in encoding.h instead of providing a path to it | Palmer Dabbelt | 5 | -4/+5 | |
| 2017-05-16 | debug: Update OpenOCD configs. | Megan Wachs | 2 | -5/+4 | |
| 2017-05-15 | Copy debug/programs to the build dir, so debug-check runs | Palmer Dabbelt | 1 | -1/+2 | |
| 2017-05-15 | Merge pull request #48 from riscv/tests | Palmer Dabbelt | 4 | -106/+117 | |
| Get the test running on Spike again | |||||
| 2017-05-15 | Disable another PRIV mention, for now | Palmer Dabbelt | 1 | -1/+2 | |
| 2017-05-15 | Disable the tests that touch PRIV, it's not implemented yet | Palmer Dabbelt | 1 | -62/+63 | |
| 2017-05-15 | Have the openocd invocation match the spike invocation | Palmer Dabbelt | 1 | -1/+1 | |
| 2017-05-15 | Disable some failing tests for now | Palmer Dabbelt | 1 | -37/+40 | |
| 2017-05-15 | Don't rely on Spike's default ISA | Palmer Dabbelt | 1 | -1/+3 | |
| 2017-05-15 | Don't use the RTOS, and do "reset halt" | Palmer Dabbelt | 1 | -3/+4 | |
| This is the most reliable way to run the tests for now. | |||||
| 2017-05-15 | Let Spike have the default amount of RAM | Palmer Dabbelt | 1 | -1/+0 | |
| Without this programs won't run. | |||||
| 2017-05-15 | Don't build openocd here, it's in riscv-tools now | Palmer Dabbelt | 1 | -1/+5 | |
| 2017-05-15 | debug: fix the make target for debug-check | Megan Wachs | 1 | -19/+2 | |
| 2017-05-15 | debug: Use consistent 'sim_cmd' argument. | Megan Wachs | 2 | -2/+2 | |
| 2017-05-14 | Merge remote-tracking branch 'origin/priv-1.10' into HEAD | Megan Wachs | 3 | -5/+12 | |
| 2017-05-05 | Check UXL in sstatus | Andrew Waterman | 2 | -5/+10 | |
| 2017-05-05 | Test that superpage PTEs trap when PPN LSBs are set | Andrew Waterman | 1 | -0/+18 | |
| 2017-05-05 | Regularize control flow in dirty-bit test | Andrew Waterman | 1 | -8/+12 | |
| 2017-05-01 | Set ELF entry point correctly | Andrew Waterman | 2 | -5/+6 | |
| 2017-04-26 | Set FS before reading F registers | Palmer Dabbelt | 1 | -0/+4 | |
| 2017-04-26 | Add abort() for benefit of benchmark code | Andrew Waterman | 1 | -0/+6 | |
| 2017-04-18 | bump OpenOCD version | Megan Wachs | 1 | -1/+1 | |
| 2017-04-18 | debug: Don't halt out of reset. It's unrealistic. Use a program which loops ↵ | Megan Wachs | 5 | -5/+20 | |
| (actually it just gets an exception anyway). | |||||
| 2017-04-18 | debug: Use RTOS OpenOCD for Spike for now. | Megan Wachs | 1 | -1/+1 | |
| 2017-04-17 | debug: Checkpoint restoring Spike functionality | Megan Wachs | 5 | -29/+51 | |
| 2017-04-17 | Merge remote-tracking branch 'origin/newprogram' into debug-0.13 | Megan Wachs | 9 | -18/+42 | |
| 2017-04-17 | Merge remote-tracking branch 'origin/priv-1.10' into HEAD | Megan Wachs | 66 | -1063/+763 | |
| 2017-04-14 | Fix illegal-instruction test when S-mode is not implemented | Andrew Waterman | 1 | -10/+14 | |
| 2017-04-14 | debug: checkpoint trying to get 64 bit programs to compile as well. | Megan Wachs | 1 | -0/+3 | |
| 2017-04-14 | debug: checkpoint of trying to get simulation tests working | Megan Wachs | 8 | -9/+29 | |
 |
index : riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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