aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2021-05-20Test multiple heterogeneous spike instances. (#338)Tim Newsome6-63/+70
2021-05-12Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: ↵SLAMET RIANTO2-0/+2
(#337) Added "#define stvec mtvec" under __MACHINE_MODE ifdef. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-05-10Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support ↵SLAMET RIANTO3-0/+52
CLIC mode. (#336) illegal.S: - After the test enters supervisor mode, check if paging is supported. - If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following: -- SFENCE.VMA causing illegal instruction trap regardless of TVM. -- Access to SATP does not trap. -- Jump to the same TSR check as regular S-mode -- End test sbreak.S & scall.S: - Before checking for scause, check if the core is in CLIC-mode (mtvec[1]). - If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value. - Otherwise, don't mask off any scause bits as in the original test. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-05-07Test daisy chained homogeneous spike instances. (#334)Tim Newsome9-40/+303
* Test debugging multiple spikes in a daisy chain. * Hugely speed up rbb_daisychain. Now 2 dual-hart spikes are less than 4x slower than a single dual-hart spike. * WIP * Test daisy chained homogeneous spike instances. For OpenOCD, this means we're checking that we can talk to multiple TAPs. Next up is heterogeneous testing. * Enable Sv48Test. Didn't mean to disable it with this commit. * Test authentication again. Another change I hadn't meant to push...
2021-04-13Add FreeRTOS smoke tests. (#333)Tim Newsome9-15/+103
* Add FreeRTOS smoke tests. Make sure that OpenOCD can access all threads in a FreeRTOS binary on single-hart RV32 and RV64. * Also test `-rtos FreeRTOS`.
2021-02-11Add early_applicable() to a few tests. (#325)Tim Newsome1-7/+8
It's faster to figure out there that the test is going to N/A.
2021-02-01Align mtvec in rv32mi-p-shamt testAndrew Waterman1-0/+1
Resolves #323
2021-02-01Prevent GCC from pattern-matching the memset implementationAndrew Waterman1-1/+1
Otherwise, we get infinite recursion. Resolves #321 Resolves #322
2021-01-25Smoketest that vl and vtype can be modified. (#320)Tim Newsome2-29/+12
2021-01-08Don't rely on the implementation-specific WFI time limit (#318)Paul Donahue1-18/+0
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset * Remove testcase that relies on the implementation-specific WFI time limit being 0.
2021-01-08Disable V extension when compiler doesn't support it. (#317)Tim Newsome1-2/+24
This allows the vast majority of these tests to work with compilers that don't support the V extension yet, which is helpful for people who aren't using a vector branch of the compiler. Specifically, this will hopefully allow us to run regression tests against OpenOCD on every change, per https://github.com/riscv/riscv-openocd/pull/563.
2021-01-07Park other harts in TranslateTest. (#313)Tim Newsome1-0/+1
This fixes an intermitten failure when running these tests.
2021-01-07Stop testing `-rtos riscv`. (#314)Tim Newsome2-23/+3
As of tomorrow that feature is officially no longer supported in OpenOCD, so stop testing it.
2021-01-04Disable rv32ua/rv64ua LR/SC test case 4 (#316)Ben Marshall1-8/+14
- After discussion in riscv/riscv-tests#315, disable this test case, as it makes implementation assumptions which are not valid with respect to the specification. - Leave code present but commented out. On branch dev/benm-disable-lrsc-test-4 Changes to be committed: modified: isa/rv64ua/lrsc.S
2020-12-31Make HiFiveUnleashed tests clean.Tim Newsome7-1/+14
HiFiveUnleashed-flash fails som address translation tests. Possibly that would be fixed when https://github.com/riscv/riscv-tests/pull/313 merges.
2020-12-18Add test for new OpenOCD `riscv info` command. (#310)Tim Newsome1-0/+13
2020-12-18Revive and expand invalid read test. (#309)Tim Newsome1-12/+19
This test would have found https://github.com/riscv/riscv-openocd/issues/559.
2020-12-16Refactor rv64ud structural test to match format of other tests (#311)Kathlene Hurt1-11/+13
* Refactored rv64ud structural test to use pass/fail macros and test numbers * More clean up so test actually jumps to fail label
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome10-1/+104
2020-12-08Add rd=x0 test case to csr test (#308)Takahiro1-0/+1
2020-12-07Fix minor typo (#307)Takahiro1-1/+1
2020-11-20Only attempt to build tests supported by compilerAndrew Waterman19-38/+6
Resolves #303
2020-11-11add zfh (float16) test case and related macros (#301)Chih-Min Chao26-0/+769
* ext: add zfh extension test case and related macro Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * build: add zfh to target Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-19use registers present on rv32e (#299)Sandeep Rajendran1-4/+4
2020-10-15bump env (#298)Sandeep Rajendran1-14/+14
2020-10-08Expose registers on all harts in openocd cfgs (#297)Samuel Obuch2-4/+10
2020-10-02Modify PMP benchmark to detect granularity (#295)Moritz Schneider1-10/+24
2020-08-31Add test for `riscv repeat_read`. (#293)Tim Newsome1-0/+34
2020-08-12Point people at a compiler that supports vectors. (#290)Tim Newsome1-1/+2
Addresses #289.
2020-08-06Add enable_rtos_riscv (#288)Tim Newsome1-0/+2
This is now required to use `-rtos riscv`. Addresses the aside mentioned in #287.
2020-07-14bump env to fix #286Andrew Waterman1-14/+14
2020-07-01Make pylint happy. (#285)Tim Newsome1-0/+1
2020-06-25Add manual hwbp test. (#283)Tim Newsome4-0/+98
Make sure OpenOCD cooperates when a user sets a trigger by writing tselect/tdata* directly.
2020-06-25Create a more sophisticated vector test (#284)Tim Newsome4-10/+248
* WIP * WIP * Vector test seems to work well with spike. * Check a0 in case the program didn't work right. * Return not applicable if compile doesn't support V
2020-05-26Test semihosting calls (#280)Tim Newsome9-5/+205
* Add a basic semihosting test. * Need to configure semihosting on each target. * WIP * Parse "cannot insert breakpoint" message. Also use sys.exit instead of exit, per new pylint's suggestion.
2020-05-18Parse "cannot insert breakpoint" message. (#279)Tim Newsome1-1/+8
Also use sys.exit instead of exit, per new pylint's suggestion.
2020-05-13Update env (#275)Paul Donahue1-5/+19
2020-04-17The HTIF device must live in its own page since it is (generally) a ↵Adrian Harris1-0/+1
bus/hardware device (#274)
2020-04-10Make TooManyHwbp more thorough. (#272)Tim Newsome1-1/+6
Test the behavior described in https://github.com/riscv/riscv-openocd/issues/76.
2020-04-10Change slen to a value that spike supports. (#271)Tim Newsome1-1/+3
2020-03-29Add debug-check-fast target forAndrew Waterman1-0/+4
This isn't appropriate for regression-testing the debug infrastructure, but is useful as a quick sanity check for unrelated CI runs, where we're just trying to make sure integration isn't totally borked.
2020-03-26Improve address translation tests (#261)Tim Newsome4-35/+59
* Improve address translation tests. Check that the mode we're testing is supported by hardware before running the test. Test with high address bits set, which catches a bug in OpenOCD. * Turn off PMP for address translation test. Otherwise it doesn't pass on HiFive Unleashed. * Run TranslateTest on random hart. Once https://github.com/riscv/riscv-openocd/pull/459 merges that will work.
2020-03-26Write a NOP program in PrivRw test. (#260)Tim Newsome2-9/+8
Otherwise it only passes intermittently when I change _start, which is very confusing.
2020-03-21Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5Andrew Waterman1-7/+7
2020-03-21Move self-modifying 'fence.i' ops to .data memory section (#269)WRansohoff1-6/+14
Co-authored-by: WRR <-@->
2020-03-19Fix comments error in fmin.S (#267)Mohanson2-4/+4
2020-03-18Spike changed --varch syntax (#257)Tim Newsome1-2/+2
This was changed by https://github.com/riscv/riscv-isa-sim/pull/417
2020-03-18Specify misa for HiFive Unleashed. (#259)Tim Newsome1-0/+2
This saves a few seconds every time I run any test.
2020-03-18Have both rs=rd and rs!=rd cases in csr.S (#263)Takahiro1-12/+15
2020-03-18Fix shamt.S header (#264)Takahiro1-2/+2
generated by cgit v1.1 at 2024-08-16 00:21:30 +0000