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Lines
2017-12-01
Ensure there are no unnamed registers.
Tim Newsome
1
-0
/
+2
2017-11-30
Merge pull request #109 from riscv/vcssim
Tim Newsome
1
-2
/
+12
2017-11-30
Clean up VcsSim init()
Tim Newsome
1
-2
/
+12
2017-11-27
Rename sbadaddr to satp
Andrew Waterman
5
-14
/
+14
2017-11-26
Rv32ud tests (#108)
Torbjørn
23
-0
/
+318
2017-11-22
Check sepc for rv64si/scall test. (#107)
Christopher Celio
1
-0
/
+4
2017-11-20
Check mtval in rv64mi-p-illegal (#104)
Andrew Waterman
1
-0
/
+11
2017-11-19
Ensure log file is fully written before reading it
Tim Newsome
1
-0
/
+1
2017-11-19
Make pylint happy.
Tim Newsome
3
-12
/
+16
2017-11-17
Merge pull request #102 from riscv/xlen_fix
Megan Wachs
1
-7
/
+8
2017-11-17
debug: Fix the XLEN command line check
xlen_fix
Megan Wachs
1
-7
/
+8
2017-11-16
Debug: Use the --32 and --64 command line arguments (#97)
Megan Wachs
3
-10
/
+17
2017-11-16
Disable PMP for PrivRw test.
Tim Newsome
1
-0
/
+5
2017-11-15
Clarify PrivTest detail.
Tim Newsome
1
-0
/
+2
2017-11-11
Make sure that code is 4-byte aligned before disabling rvc (#100)
Andrew Waterman
4
-1
/
+5
2017-11-09
Make rv64mi-p-ecall work when U-mode is not present
Andrew Waterman
1
-1
/
+17
2017-11-09
Use mstatus.MPP to check existence of U-mode
Andrew Waterman
1
-5
/
+6
2017-11-02
Add --print-log-names to print temp log names ASAP
Tim Newsome
2
-5
/
+17
2017-11-02
Ensure gdb connection failures end up in main log.
Tim Newsome
1
-9
/
+18
2017-11-02
debug: Need to apply remotetimeout before connecting to remote target (#94)
Megan Wachs
1
-6
/
+7
2017-11-01
SBREAK test now checks EPC value. (#92)
Christopher Celio
1
-0
/
+4
2017-11-01
Make pylint 1.6.5 happy.
Tim Newsome
4
-6
/
+5
2017-11-01
Test register aliases in the simple register tests
Tim Newsome
1
-9
/
+17
2017-11-01
Fix MulticoreRegTest.
Tim Newsome
2
-59
/
+65
2017-10-31
Merge pull request #90 from richardxia/comment-out-multicore-reg-test
Palmer Dabbelt
1
-57
/
+58
2017-10-31
Temporarily comment out MulticoreRegTest due to flakiness.
Richard Xia
1
-57
/
+58
2017-10-30
Remove cache miss test from last AMO test. (#88)
Richard Xia
1
-17
/
+0
2017-10-30
Declare trap handlers as global symbols. (#87)
Richard Xia
8
-0
/
+9
2017-10-26
Verify that mtval/stval is written correctly on misaligned fetch
Andrew Waterman
1
-1
/
+9
2017-10-26
Fix rv64mi-csr for the case where U-mode is not available. (#86)
Richard Xia
1
-0
/
+16
2017-10-24
Increase dual-core RV64 timeouts.
Tim Newsome
2
-2
/
+2
2017-10-19
Get helpful gdb output in MemTestBlock.
Tim Newsome
1
-1
/
+4
2017-10-12
Pay attention to server_timeout_sec
Tim Newsome
1
-2
/
+3
2017-10-04
Resurrect priv tests.
Tim Newsome
1
-52
/
+51
2017-10-04
Merge pull request #79 from riscv/multigdb
Tim Newsome
13
-96
/
+236
2017-09-29
Make ExamineTarget multi-core aware.
Tim Newsome
1
-18
/
+23
2017-09-29
Fix tests to work in multi-gdb mode.
Tim Newsome
13
-87
/
+236
2017-09-22
Remove unused function.
Tim Newsome
1
-9
/
+0
2017-09-21
Add coverage for single-core non-rtos OpenOCD.
Tim Newsome
4
-3
/
+19
2017-09-19
Allow multiple reset vectors.
Tim Newsome
4
-3
/
+8
2017-09-19
Link against libm for fma()
Andrew Waterman
1
-1
/
+1
2017-09-19
Merge pull request #76 from riscv/multicore
Tim Newsome
3
-14
/
+28
2017-09-19
Forgot to commit this earlier.
Tim Newsome
1
-0
/
+20
2017-09-18
Add interrupts to MulticoreRunHaltStepiTest.
Tim Newsome
4
-16
/
+29
2017-09-15
Don't read entire log into RAM just to print it.
Tim Newsome
1
-2
/
+1
2017-09-14
misa is stored in the hart now, not the target
Tim Newsome
1
-6
/
+6
2017-09-14
When spike fails to launch, display its output.
Tim Newsome
1
-21
/
+29
2017-09-14
Test debugging code with interrupts.
Tim Newsome
5
-4
/
+80
2017-09-14
Call postMortem() when a test fails.
Tim Newsome
2
-8
/
+15
2017-09-14
Clarify timeout units.
Tim Newsome
1
-0
/
+1
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