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2017-12-01Ensure there are no unnamed registers.Tim Newsome1-0/+2
2017-11-30Merge pull request #109 from riscv/vcssimTim Newsome1-2/+12
2017-11-30Clean up VcsSim init()Tim Newsome1-2/+12
2017-11-27Rename sbadaddr to satpAndrew Waterman5-14/+14
2017-11-26Rv32ud tests (#108)Torbjørn23-0/+318
2017-11-22Check sepc for rv64si/scall test. (#107)Christopher Celio1-0/+4
2017-11-20Check mtval in rv64mi-p-illegal (#104)Andrew Waterman1-0/+11
2017-11-19Ensure log file is fully written before reading itTim Newsome1-0/+1
2017-11-19Make pylint happy.Tim Newsome3-12/+16
2017-11-17Merge pull request #102 from riscv/xlen_fixMegan Wachs1-7/+8
2017-11-17debug: Fix the XLEN command line checkxlen_fixMegan Wachs1-7/+8
2017-11-16Debug: Use the --32 and --64 command line arguments (#97)Megan Wachs3-10/+17
2017-11-16Disable PMP for PrivRw test.Tim Newsome1-0/+5
2017-11-15Clarify PrivTest detail.Tim Newsome1-0/+2
2017-11-11Make sure that code is 4-byte aligned before disabling rvc (#100)Andrew Waterman4-1/+5
2017-11-09Make rv64mi-p-ecall work when U-mode is not presentAndrew Waterman1-1/+17
2017-11-09Use mstatus.MPP to check existence of U-modeAndrew Waterman1-5/+6
2017-11-02Add --print-log-names to print temp log names ASAPTim Newsome2-5/+17
2017-11-02Ensure gdb connection failures end up in main log.Tim Newsome1-9/+18
2017-11-02debug: Need to apply remotetimeout before connecting to remote target (#94)Megan Wachs1-6/+7
2017-11-01SBREAK test now checks EPC value. (#92)Christopher Celio1-0/+4
2017-11-01Make pylint 1.6.5 happy.Tim Newsome4-6/+5
2017-11-01Test register aliases in the simple register testsTim Newsome1-9/+17
2017-11-01Fix MulticoreRegTest.Tim Newsome2-59/+65
2017-10-31Merge pull request #90 from richardxia/comment-out-multicore-reg-testPalmer Dabbelt1-57/+58
2017-10-31Temporarily comment out MulticoreRegTest due to flakiness.Richard Xia1-57/+58
2017-10-30Remove cache miss test from last AMO test. (#88)Richard Xia1-17/+0
2017-10-30Declare trap handlers as global symbols. (#87)Richard Xia8-0/+9
2017-10-26Verify that mtval/stval is written correctly on misaligned fetchAndrew Waterman1-1/+9
2017-10-26Fix rv64mi-csr for the case where U-mode is not available. (#86)Richard Xia1-0/+16
2017-10-24Increase dual-core RV64 timeouts.Tim Newsome2-2/+2
2017-10-19Get helpful gdb output in MemTestBlock.Tim Newsome1-1/+4
2017-10-12Pay attention to server_timeout_secTim Newsome1-2/+3
2017-10-04Resurrect priv tests.Tim Newsome1-52/+51
2017-10-04Merge pull request #79 from riscv/multigdbTim Newsome13-96/+236
2017-09-29Make ExamineTarget multi-core aware.Tim Newsome1-18/+23
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome13-87/+236
2017-09-22Remove unused function.Tim Newsome1-9/+0
2017-09-21Add coverage for single-core non-rtos OpenOCD.Tim Newsome4-3/+19
2017-09-19Allow multiple reset vectors.Tim Newsome4-3/+8
2017-09-19Link against libm for fma()Andrew Waterman1-1/+1
2017-09-19Merge pull request #76 from riscv/multicoreTim Newsome3-14/+28
2017-09-19Forgot to commit this earlier.Tim Newsome1-0/+20
2017-09-18Add interrupts to MulticoreRunHaltStepiTest.Tim Newsome4-16/+29
2017-09-15Don't read entire log into RAM just to print it.Tim Newsome1-2/+1
2017-09-14misa is stored in the hart now, not the targetTim Newsome1-6/+6
2017-09-14When spike fails to launch, display its output.Tim Newsome1-21/+29
2017-09-14Test debugging code with interrupts.Tim Newsome5-4/+80
2017-09-14Call postMortem() when a test fails.Tim Newsome2-8/+15
2017-09-14Clarify timeout units.Tim Newsome1-0/+1
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